Re: [libre-riscv-dev] cache SRAM organisation
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 26 Mar 2020 21:28:32 +0000 (21:28 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Thu, 26 Mar 2020 21:29:06 +0000 (21:29 +0000)
3a/a08a392c0661db5719000c86db7d06a43756c5 [new file with mode: 0644]

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+In-Reply-To: <7b5a312befec67dbf14d31f5bb4c418c8784e787.camel@fibraservi.eu>
+From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date: Thu, 26 Mar 2020 21:28:32 +0000
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+Message-ID: <CAPweEDx9YH=0DWviRYJySR9++n-Nd88ZHkRb8EkWhah3x4MbeQ@mail.gmail.com>
+To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
+Subject: Re: [libre-riscv-dev] cache SRAM organisation
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