boards/platforms/ulx3s: fix default clock

diff --git a/litex/boards/platforms/ulx3s.py b/litex/boards/platforms/ulx3s.py
index ed1bcab6f90eef3be0c0205e06150d40ebcb2a4e..2a7f6d843d72d077964273e9ae9e15b4feb8c352 100644 (file)
--- a/litex/boards/platforms/ulx3s.py
+++ b/litex/boards/platforms/ulx3s.py
@@ -68,8 +68,8 @@ _io = [
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(LatticePlatform):
-    default_clk_name = "clk100"
-    default_clk_period = 10
+    default_clk_name = "clk25"
+    default_clk_period = 40
 
     def __init__(self, device="LFE5U-45F", **kwargs):
         LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)