Register outputs on loadstore1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/loadstore1.vhdl b/loadstore1.vhdl
index bf006d92d4e518e5f7d278645740334c814b5ec6..f35b64d4132d90f681b708a5d7a8e3acba8bbbc6 100644 (file)
--- a/loadstore1.vhdl
+++ b/loadstore1.vhdl
@@ -13,36 +13,46 @@ entity loadstore1 is
                clk   : in std_ulogic;
 
                l_in  : in Decode2ToLoadstore1Type;
+
                l_out : out Loadstore1ToLoadstore2Type
        );
 end loadstore1;
 
 architecture behave of loadstore1 is
-       signal l       : Decode2ToLoadstore1Type;
+       signal r, rin : Loadstore1ToLoadstore2Type;
        signal lsu_sum : std_ulogic_vector(63 downto 0);
 begin
        -- Calculate the address in the first cycle
-       lsu_sum <= std_ulogic_vector(unsigned(l.addr1) + unsigned(l.addr2)) when l.valid = '1' else (others => '0');
+       lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
 
        loadstore1_0: process(clk)
        begin
                if rising_edge(clk) then
-                       l <= l_in;
+                       r <= rin;
                end if;
        end process;
 
        loadstore1_1: process(all)
+               variable v : Loadstore1ToLoadstore2Type;
        begin
-               l_out.valid <= l.valid;
-               l_out.load <= l.load;
-               l_out.data <= l.data;
-               l_out.write_reg <= l.write_reg;
-               l_out.length <= l.length;
-               l_out.byte_reverse <= l.byte_reverse;
-               l_out.sign_extend <= l.sign_extend;
-               l_out.update <= l.update;
-               l_out.update_reg <= l.update_reg;
-
-               l_out.addr <= lsu_sum;
+               v := r;
+
+               v.valid := l_in.valid;
+               v.load := l_in.load;
+               v.data := l_in.data;
+               v.write_reg := l_in.write_reg;
+               v.length := l_in.length;
+               v.byte_reverse := l_in.byte_reverse;
+               v.sign_extend := l_in.sign_extend;
+               v.update := l_in.update;
+               v.update_reg := l_in.update_reg;
+
+               v.addr := lsu_sum;
+
+               -- Update registers
+               rin <= v;
+
+                -- Update outputs
+                l_out <= v;
        end process;
 end;