#define __ARCH_SPARC_PAGETABLE_HH__
#include "arch/sparc/isa_traits.hh"
+#include "base/bitfield.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
if (type == sun4u)
entry4u = entry;
else {
- uint64_t entry4u = 0;
- entry4u |= entry & ULL(0x8000000000000000); //valid
- entry4u |= (entry & 0x3) << 61; //size[1:0]
- entry4u |= (entry & ULL(0x4000000000000000)) >> 2; //nfo
- entry4u |= (entry & 0x1000) << 47; //ie
- //entry4u |= (entry & 0x3F00000000000000) >> 7; //soft2
- entry4u |= (entry & 0x4) << 48; //size[2]
- //diag?
- entry4u |= (entry & ULL(0x0000FFFFFFFFE000)); //paddr
- entry4u |= (entry & 0x400) >> 5; //cp
- entry4u |= (entry & 0x200) >> 5; //cv
- entry4u |= (entry & 0x800) >> 8; //e
- entry4u |= (entry & 0x100) >> 6; //p
- entry4u |= (entry & 0x40) >> 5; //w
+ entry4u = 0;
+ entry4u |= mbits(entry,63,63); //valid
+ entry4u |= bits(entry,1,0) << 61; //size[1:0]
+ entry4u |= bits(entry,62,62) << 60; //nfo
+ entry4u |= bits(entry,12,12) << 59; //ie
+ entry4u |= bits(entry,2,2) << 48; //size[2]
+ entry4u |= mbits(entry,39,13); //paddr
+ entry4u |= bits(entry,61,61) << 6;; // locked
+ entry4u |= bits(entry,10,10) << 5; //cp
+ entry4u |= bits(entry,9,9) << 4; //cv
+ entry4u |= bits(entry,11,11) << 3; //e
+ entry4u |= bits(entry,8,8) << 2; //p
+ entry4u |= bits(entry,6,6) << 1; //w
}
}
const PageTableEntry &operator=(const PageTableEntry &e)
{ populated = true; entry4u = e.entry4u; return *this; }
- bool valid() const { return entry4u & ULL(0x8000000000000000) && populated; }
+ bool valid() const { return bits(entry4u,63,63) && populated; }
uint8_t _size() const { assert(populated);
- return ((entry4u & 0x6) >> 61) |
- ((entry4u & ULL(0x000080000000000)) >> 46); }
- Addr size() const { return pageSizes[_size()]; }
- bool ie() const { return entry4u >> 59 & 0x1; }
- Addr pfn() const { assert(populated);
- return entry4u >> 13 & ULL(0xFFFFFFFFFF); }
- Addr paddr() const { assert(populated);
- return entry4u & ULL(0x0000FFFFFFFFE000); }
- bool locked() const { assert(populated);
- return entry4u & 0x40; }
- bool cv() const { assert(populated);
- return entry4u & 0x10; }
- bool cp() const { assert(populated);
- return entry4u & 0x20; }
- bool priv() const { assert(populated);
- return entry4u & 0x4; }
- bool writable() const { assert(populated);
- return entry4u & 0x2; }
- bool nofault() const { assert(populated);
- return entry4u & ULL(0x1000000000000000); }
- bool sideffect() const { assert(populated);
- return entry4u & 0x8; }
+ return bits(entry4u, 62,61) |
+ bits(entry4u, 48,48) << 2; }
+ Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
+ bool ie() const { return bits(entry4u, 59,59); }
+ Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
+ Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
+ bool locked() const { assert(populated); return bits(entry4u,6,6); }
+ bool cv() const { assert(populated); return bits(entry4u,4,4); }
+ bool cp() const { assert(populated); return bits(entry4u,5,5); }
+ bool priv() const { assert(populated); return bits(entry4u,2,2); }
+ bool writable() const { assert(populated); return bits(entry4u,1,1); }
+ bool nofault() const { assert(populated); return bits(entry4u,60,60); }
+ bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
};
struct TlbRange {
void
TLB::insert(Addr va, int partition_id, int context_id, bool real,
- const PageTableEntry& PTE)
+ const PageTableEntry& PTE, int entry)
{
MapIter i;
- TlbEntry *new_entry;
+ TlbEntry *new_entry = NULL;
+ int x;
- DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n",
- va, partition_id, context_id, (int)real);
+ DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n",
+ va, PTE.paddr(), partition_id, context_id, (int)real);
- int x = -1;
- for (x = 0; x < size; x++) {
- if (!tlb[x].valid || !tlb[x].used) {
- new_entry = &tlb[x];
- break;
+ if (entry != -1) {
+ assert(entry < size && entry >= 0);
+ new_entry = &tlb[entry];
+ } else {
+ for (x = 0; x < size; x++) {
+ if (!tlb[x].valid || !tlb[x].used) {
+ new_entry = &tlb[x];
+ break;
+ }
}
}
// Update the last ently if their all locked
- if (x == -1)
- x = size - 1;
+ if (!new_entry)
+ new_entry = &tlb[size-1];
assert(PTE.valid());
new_entry->range.va = va;
DPRINTF(TLB, "TLB: No valid entry found\n");
return NULL;
}
- DPRINTF(TLB, "TLB: Valid entry found\n");
// Mark the entries used bit and clear other used bits in needed
t = i->second;
+ DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
+ t->pte.size());
if (!t->used) {
t->used = true;
usedEntries++;
return t;
}
+void
+TLB::dumpAll()
+{
+ for (int x = 0; x < size; x++) {
+ if (tlb[x].valid) {
+ DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
+ x, tlb[x].range.partitionId, tlb[x].range.contextId,
+ tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
+ tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
+ }
+ }
+}
void
TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
sfsr |= 1 << 6;
sfsr |= ft << 7;
sfsr |= asi << 16;
- tc->setMiscReg(reg, sfsr);
+ tc->setMiscRegWithEffect(reg, sfsr);
}
+void
+TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
+{
+ tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
+}
void
ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
}
+void
+ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
+{
+ TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
+}
+
void
DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
bool se, FaultTypes ft, int asi)
DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
a, (int)write, ct, ft, asi);
TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
- tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
+ tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
+}
+
+ void
+DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
+{
+ TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
}
+
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc)
{
}
// If the asi is unaligned trap
- if (vaddr & 0x7) {
+ if (vaddr & req->getSize()-1) {
writeSfsr(tc, false, ct, false, OtherFault, asi);
return new MemAddressNotAligned;
}
return new InstructionAccessException;
}
- req->setPaddr(e->pte.paddr() & ~e->pte.size() |
- req->getVaddr() & e->pte.size());
+ req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
+ req->getVaddr() & e->pte.size()-1 );
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
return NoFault;
}
return new DataAccessException;
}
- }
-
- // If the asi is unaligned trap
- if (vaddr & size-1) {
- writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
- return new MemAddressNotAligned;
- }
-
- if (addr_mask)
- vaddr = vaddr & VAddrAMask;
-
- if (!validVirtualAddress(vaddr, addr_mask)) {
- writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
- return new DataAccessException;
+ } else if (hpriv) {
+ if (asi == ASI_P) {
+ ct = Primary;
+ context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
+ goto continueDtbFlow;
+ }
}
if (!implicit) {
panic("Accessing ASI %#X. Should we?\n", asi);
}
+continueDtbFlow:
+ // If the asi is unaligned trap
+ if (vaddr & size-1) {
+ writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
+ return new MemAddressNotAligned;
+ }
+
+ if (addr_mask)
+ vaddr = vaddr & VAddrAMask;
+
+ if (!validVirtualAddress(vaddr, addr_mask)) {
+ writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
+ return new DataAccessException;
+ }
+
+
if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
real = true;
context = 0;
return new DataAccessException;
}
- req->setPaddr(e->pte.paddr() & ~e->pte.size() |
- req->getVaddr() & e->pte.size());
+ req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
+ req->getVaddr() & e->pte.size()-1);
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
return NoFault;
/** Normal flow ends here. */
assert(va == 0);
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
break;
+ case ASI_SPARC_ERROR_STATUS_REG:
+ warn("returning 0 for SPARC ERROR regsiter read\n");
+ pkt->set(0);
+ break;
case ASI_HYP_SCRATCHPAD:
case ASI_SCRATCHPAD:
pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
break;
+ case ASI_IMMU:
+ switch (va) {
+ case 0x30:
+ pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
+ break;
+ default:
+ goto doMmuReadError;
+ }
+ break;
case ASI_DMMU:
switch (va) {
+ case 0x30:
+ pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
+ break;
case 0x80:
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
break;
Addr va = pkt->getAddr();
ASI asi = (ASI)pkt->req->getAsi();
+ Addr ta_insert;
+ Addr va_insert;
+ Addr ct_insert;
+ int part_insert;
+ int entry_insert = -1;
+ bool real_insert;
+ PageTableEntry pte;
+
DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
(uint32_t)asi, va, data);
case ASI_SCRATCHPAD:
tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
break;
+ case ASI_IMMU:
+ switch (va) {
+ case 0x30:
+ tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
+ break;
+ default:
+ goto doMmuWriteError;
+ }
+ break;
+ case ASI_ITLB_DATA_ACCESS_REG:
+ entry_insert = bits(va, 8,3);
+ case ASI_ITLB_DATA_IN_REG:
+ assert(entry_insert != -1 || mbits(va,10,9) == va);
+ ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+ va_insert = mbits(ta_insert, 63,13);
+ ct_insert = mbits(ta_insert, 12,0);
+ part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+ real_insert = bits(va, 9,9);
+ pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
+ PageTableEntry::sun4u);
+ tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
+ pte, entry_insert);
+ break;
+ case ASI_DTLB_DATA_ACCESS_REG:
+ entry_insert = bits(va, 8,3);
+ case ASI_DTLB_DATA_IN_REG:
+ assert(entry_insert != -1 || mbits(va,10,9) == va);
+ ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+ va_insert = mbits(ta_insert, 63,13);
+ ct_insert = mbits(ta_insert, 12,0);
+ part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+ real_insert = bits(va, 9,9);
+ pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
+ PageTableEntry::sun4u);
+ insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
+ break;
case ASI_DMMU:
switch (va) {
+ case 0x30:
+ tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
+ break;
case 0x80:
tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
break;
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