cpu,stats: Update stats style for base.hh and base.cc

Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36297
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index b524ad11b07d9516dcbcbc2e9c11c1e98b1034f7..0c998be4cc0c9d0778c6bb0be8294ee41039727b 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -133,6 +133,7 @@ BaseCPU::BaseCPU(const Params &p, bool is_checker)
       previousCycle(0), previousState(CPU_STATE_SLEEP),
       functionTraceStream(nullptr), currentFunctionStart(0),
       currentFunctionEnd(0), functionEntryTick(0),
+      baseStats(this),
       addressMonitor(p.numThreads),
       syscallRetryLatency(p.syscallRetryLatency),
       pwrGatingLatency(p.pwr_gating_latency),
@@ -368,6 +369,16 @@ BaseCPU::probeInstCommit(const StaticInstPtr &inst, Addr pc)
         ppRetiredBranches->notify(1);
 }
 
+BaseCPU::
+BaseCPUStats::BaseCPUStats(Stats::Group *parent)
+    : Stats::Group(parent),
+      ADD_STAT(numCycles, "Number of cpu cycles simulated"),
+      ADD_STAT(numWorkItemsStarted, "Number of work items this cpu started"),
+      ADD_STAT(numWorkItemsCompleted,
+               "Number of work items this cpu completed")
+{
+}
+
 void
 BaseCPU::regStats()
 {
@@ -381,21 +392,6 @@ BaseCPU::regStats()
 
     using namespace Stats;
 
-    numCycles
-        .name(name() + ".numCycles")
-        .desc("number of cpu cycles simulated")
-        ;
-
-    numWorkItemsStarted
-        .name(name() + ".numWorkItemsStarted")
-        .desc("number of work items this cpu started")
-        ;
-
-    numWorkItemsCompleted
-        .name(name() + ".numWorkItemsCompleted")
-        .desc("number of work items this cpu completed")
-        ;
-
     int size = threadContexts.size();
     if (size > 1) {
         for (int i = 0; i < size; ++i) {

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c7932955681f881fa12188ec4c82a041a08203e3..3d09959bdae4c034a4f1e7a9628572987fe4c9d8 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -223,8 +223,8 @@ class BaseCPU : public ClockedObject
     uint32_t getPid() const { return _pid; }
     void setPid(uint32_t pid) { _pid = pid; }
 
-    inline void workItemBegin() { numWorkItemsStarted++; }
-    inline void workItemEnd() { numWorkItemsCompleted++; }
+    inline void workItemBegin() { baseStats.numWorkItemsStarted++; }
+    inline void workItemEnd() { baseStats.numWorkItemsCompleted++; }
     // @todo remove me after debugging with legion done
     Tick instCount() { return instCnt; }
 
@@ -604,10 +604,14 @@ class BaseCPU : public ClockedObject
     }
 
   public:
-    // Number of CPU cycles simulated
-    Stats::Scalar numCycles;
-    Stats::Scalar numWorkItemsStarted;
-    Stats::Scalar numWorkItemsCompleted;
+    struct BaseCPUStats : public Stats::Group
+    {
+        BaseCPUStats(Stats::Group *parent);
+        // Number of CPU cycles simulated
+        Stats::Scalar numCycles;
+        Stats::Scalar numWorkItemsStarted;
+        Stats::Scalar numWorkItemsCompleted;
+    } baseStats;
 
   private:
     std::vector<AddressMonitor> addressMonitor;

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index a4a63234295cc92fa2c0a86760e515ba5baf5e2b..70dc451613180abd7f99f31159c76c7147b943d2 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -196,7 +196,7 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst)
         while (!result.empty()) {
             result.pop();
         }
-        numCycles++;
+        baseStats.numCycles++;
 
         Fault fault = NoFault;
 

diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index f339ec0fcc94b41a0dd06463154838882854c708..cb0b4bb0d506cb433113dcec1c667a3b5433d9aa 100644 (file)
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -491,7 +491,8 @@ BaseKvmCPU::activateContext(ThreadID thread_num)
     assert(_status == Idle);
     assert(!tickEvent.scheduled());
 
-    numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
+    baseStats.numCycles +=
+        ticksToCycles(thread->lastActivate - thread->lastSuspend);
 
     schedule(tickEvent, clockEdge(Cycles(0)));
     _status = Running;
@@ -762,7 +763,7 @@ BaseKvmCPU::kvmRun(Tick ticks)
         ticksExecuted = runTimer->ticksFromHostCycles(hostCyclesExecuted);
 
         /* Update statistics */
-        numCycles += simCyclesExecuted;;
+        baseStats.numCycles += simCyclesExecuted;;
         stats.committedInsts += instsExecuted;
         ctrInsts += instsExecuted;
         system->totalNumInsts += instsExecuted;

diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index d3f915700450e9546619c4b4547f2bda72083311..78c2020623c7503e84a3f46aa1b841fc31344f5a 100644 (file)
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -52,7 +52,7 @@ namespace Minor
 {
 
 Pipeline::Pipeline(MinorCPU &cpu_, const MinorCPUParams &params) :
-    Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
+    Ticked(cpu_, &(cpu_.BaseCPU::baseStats.numCycles)),
     cpu(cpu_),
     allow_idling(params.enableIdling),
     f1ToF2(cpu.name() + ".f1ToF2", "lines",

diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc
index b43a4a1d695987096cb9575a4be9a03ccb3fb6c7..cf28b0f065e86aba8460599a522136d335022dfe 100644 (file)
--- a/src/cpu/minor/stats.cc
+++ b/src/cpu/minor/stats.cc
@@ -59,10 +59,10 @@ MinorStats::MinorStats(BaseCPU *base_cpu)
     quiesceCycles.prereq(quiesceCycles);
 
     cpi.precision(6);
-    cpi = base_cpu->numCycles / numInsts;
+    cpi = base_cpu->baseStats.numCycles / numInsts;
 
     ipc.precision(6);
-    ipc = numInsts / base_cpu->numCycles;
+    ipc = numInsts / base_cpu->baseStats.numCycles;
 
     committedInstType
         .init(base_cpu->numThreads, Enums::Num_OpClass)

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index de14ecbebd6ef5488175333f08f60dca5055a3a5..c67ee64b448f262655a43c5ac222297100d756c7 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -433,19 +433,19 @@ FullO3CPUStats::FullO3CPUStats(FullO3CPU *cpu)
 
     cpi
         .precision(6);
-    cpi = cpu->numCycles / committedInsts;
+    cpi = cpu->baseStats.numCycles / committedInsts;
 
     totalCpi
         .precision(6);
-    totalCpi = cpu->numCycles / sum(committedInsts);
+    totalCpi = cpu->baseStats.numCycles / sum(committedInsts);
 
     ipc
         .precision(6);
-    ipc =  committedInsts / cpu->numCycles;
+    ipc = committedInsts / cpu->baseStats.numCycles;
 
     totalIpc
         .precision(6);
-    totalIpc =  sum(committedInsts) / cpu->numCycles;
+    totalIpc = sum(committedInsts) / cpu->baseStats.numCycles;
 
     intRegfileReads
         .prereq(intRegfileReads);
@@ -492,7 +492,7 @@ FullO3CPU<Impl>::tick()
     assert(!switchedOut());
     assert(drainState() != DrainState::Drained);
 
-    ++numCycles;
+    ++baseStats.numCycles;
     updateCycleCounters(BaseCPU::CPU_STATE_ON);
 
 //    activity = false;
@@ -1665,7 +1665,7 @@ FullO3CPU<Impl>::wakeCPU()
     if (cycles > 1) {
         --cycles;
         cpuStats.idleCycles += cycles;
-        numCycles += cycles;
+        baseStats.numCycles += cycles;
     }
 
     schedule(tickEvent, clockEdge());

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e5cf78645b68c3d7c3d600f401558a59e8a3978b..6f03e78c9afc67de1869251df4f0e78b6c76d069 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -162,44 +162,45 @@ DefaultFetch<Impl>::
 FetchStatGroup::FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch)
     : Stats::Group(cpu, "fetch"),
     ADD_STAT(icacheStallCycles,
-     "Number of cycles fetch is stalled on an Icache miss"),
+             "Number of cycles fetch is stalled on an Icache miss"),
     ADD_STAT(insts, "Number of instructions fetch has processed"),
     ADD_STAT(branches, "Number of branches that fetch encountered"),
     ADD_STAT(predictedBranches,
-     "Number of branches that fetch has predicted taken"),
+             "Number of branches that fetch has predicted taken"),
     ADD_STAT(cycles,
-     "Number of cycles fetch has run and was not squashing or blocked"),
+             "Number of cycles fetch has run and was not squashing or "
+             "blocked"),
     ADD_STAT(squashCycles, "Number of cycles fetch has spent squashing"),
     ADD_STAT(tlbCycles,
-     "Number of cycles fetch has spent waiting for tlb"),
+             "Number of cycles fetch has spent waiting for tlb"),
     ADD_STAT(idleCycles, "Number of cycles fetch was idle"),
     ADD_STAT(blockedCycles, "Number of cycles fetch has spent blocked"),
     ADD_STAT(miscStallCycles,
-     "Number of cycles fetch has spent waiting on interrupts,"
-      "or bad addresses, or out of MSHRs"),
+             "Number of cycles fetch has spent waiting on interrupts, "
+             "or bad addresses, or out of MSHRs"),
     ADD_STAT(pendingDrainCycles,
-     "Number of cycles fetch has spent waiting on pipes to drain"),
+             "Number of cycles fetch has spent waiting on pipes to drain"),
     ADD_STAT(noActiveThreadStallCycles,
-     "Number of stall cycles due to no active thread to fetch from"),
+             "Number of stall cycles due to no active thread to fetch from"),
     ADD_STAT(pendingTrapStallCycles,
-     "Number of stall cycles due to pending traps"),
+             "Number of stall cycles due to pending traps"),
     ADD_STAT(pendingQuiesceStallCycles,
-     "Number of stall cycles due to pending quiesce instructions"),
+             "Number of stall cycles due to pending quiesce instructions"),
     ADD_STAT(icacheWaitRetryStallCycles,
-     "Number of stall cycles due to full MSHR"),
+             "Number of stall cycles due to full MSHR"),
     ADD_STAT(cacheLines, "Number of cache lines fetched"),
     ADD_STAT(icacheSquashes,
-     "Number of outstanding Icache misses that were squashed"),
+             "Number of outstanding Icache misses that were squashed"),
     ADD_STAT(tlbSquashes,
-     "Number of outstanding ITLB misses that were squashed"),
+             "Number of outstanding ITLB misses that were squashed"),
     ADD_STAT(nisnDist,
-     "Number of instructions fetched each cycle (Total)"),
+             "Number of instructions fetched each cycle (Total)"),
     ADD_STAT(idleRate, "Percent of cycles fetch was idle",
-     idleCycles * 100 / cpu->numCycles),
+             idleCycles * 100 / cpu->baseStats.numCycles),
     ADD_STAT(branchRate, "Number of branch fetches per cycle",
-     branches / cpu->numCycles),
+             branches / cpu->baseStats.numCycles),
     ADD_STAT(rate, "Number of inst fetches per cycle",
-     insts / cpu->numCycles)
+             insts / cpu->baseStats.numCycles)
 {
         icacheStallCycles
             .prereq(icacheStallCycles);

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index a50a94a69710caf5137efe988dd2979e04290129..9e56ed097221722e612ad57e871f172636c3b83b 100644 (file)
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -193,7 +193,7 @@ IEWStats::IEWStats(O3CPU *cpu)
 
     wbRate
         .flags(Stats::total);
-    wbRate = writebackCount / cpu->numCycles;
+    wbRate = writebackCount / cpu->baseStats.numCycles;
 
     wbFanout
         .flags(Stats::total);
@@ -213,7 +213,8 @@ ExecutedInstStats::ExecutedInstStats(O3CPU *cpu)
     ADD_STAT(numRefs, "Number of memory reference insts executed"),
     ADD_STAT(numBranches, "Number of branches executed"),
     ADD_STAT(numStoreInsts, "Number of stores executed"),
-    ADD_STAT(numRate, "Inst execution rate", numInsts / cpu->numCycles)
+    ADD_STAT(numRate, "Inst execution rate",
+             numInsts / cpu->baseStats.numCycles)
 {
     numLoadInsts
         .init(cpu->numThreads)

diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 44af65486b470491dee6df71687253ca795d9f40..3538b4382aa897b909082aa26d1c655623c73402 100644 (file)
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -199,7 +199,8 @@ IQStats::IQStats(O3CPU *cpu, const unsigned &total_width)
     ADD_STAT(numIssuedDist, "Number of insts issued each cycle"),
     ADD_STAT(statFuBusy, "attempts to use FU when none available"),
     ADD_STAT(statIssuedInstType, "Type of FU issued"),
-    ADD_STAT(issueRate, "Inst issue rate", instsIssued / cpu->numCycles),
+    ADD_STAT(issueRate, "Inst issue rate",
+             instsIssued / cpu->baseStats.numCycles),
     ADD_STAT(fuBusy, "FU busy when requested"),
     ADD_STAT(fuBusyRate, "FU busy rate (busy events/executed inst)")
 {

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 74f6cbee1d78e30eb294a330f01d61a65c73cc6a..c3cbd496aa6bd730459da380be6032c66bc2aa9c 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -228,7 +228,7 @@ AtomicSimpleCPU::activateContext(ThreadID thread_num)
     threadInfo[thread_num]->execContextStats.notIdleFraction = 1;
     Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate -
                                  threadInfo[thread_num]->thread->lastSuspend);
-    numCycles += delta;
+    baseStats.numCycles += delta;
 
     if (!tickEvent.scheduled()) {
         //Make sure ticks are still on multiples of cycles
@@ -633,7 +633,7 @@ AtomicSimpleCPU::tick()
     Tick latency = 0;
 
     for (int i = 0; i < width || locked; ++i) {
-        numCycles++;
+        baseStats.numCycles++;
         updateCycleCounters(BaseCPU::CPU_STATE_ON);
 
         if (!curStaticInst || !curStaticInst->isDelayedCommit()) {

diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 3d47e6378d80e3d196623e77637fc64e1ae51db8..0212e7052d3fdd86aaf4e9fb6898e28adf2e9cd1 100644 (file)
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -157,8 +157,8 @@ class SimpleExecContext : public ExecContext {
             }
 
             idleFraction = Stats::constant(1.0) - notIdleFraction;
-            numIdleCycles = idleFraction * cpu->numCycles;
-            numBusyCycles = notIdleFraction * cpu->numCycles;
+            numIdleCycles = idleFraction * cpu->baseStats.numCycles;
+            numBusyCycles = notIdleFraction * cpu->baseStats.numCycles;
 
             numBranches
                 .prereq(numBranches);

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7f3c1cdde5d433f959309134232b64be13a91338..5e9eb92d7a314b6c99a3b92807c849de4fed339f 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1078,7 +1078,7 @@ TimingSimpleCPU::updateCycleCounts()
 {
     const Cycles delta(curCycle() - previousCycle);
 
-    numCycles += delta;
+    baseStats.numCycles += delta;
 
     previousCycle = curCycle();
 }

diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 57f249707f8312750a54771e2d9a0da48c31ee5d..9c39e59f20a51fd154f59f578c3026e9ee4a018a 100644 (file)
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -175,7 +175,7 @@ TraceCPU::schedDcacheNext()
     DPRINTF(TraceCPUData, "DcacheGen event.\n");
 
     // Update stat for numCycles
-    numCycles = clockEdge() / clockPeriod();
+    baseStats.numCycles = clockEdge() / clockPeriod();
 
     dcacheGen.execute();
     if (dcacheGen.isExecComplete()) {
@@ -211,7 +211,7 @@ TraceCPU::checkAndSchedExitEvent()
      "Number of events scheduled to trigger instruction request generator"),
     ADD_STAT(numOps, "Number of micro-ops simulated by the Trace CPU"),
     ADD_STAT(cpi, "Cycles per micro-op used as a proxy for CPI",
-     trace->numCycles / numOps)
+     trace->baseStats.numCycles / numOps)
 {
         cpi.precision(6);
 }