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diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn
index d47bf18cf10dd107a957a99f2f4e17de89691563..c8571bd549ad4ab9953f495f751368f304804463 100644 (file)
--- a/openpower/sv/twin_butterfly.mdwn
+++ b/openpower/sv/twin_butterfly.mdwn
@@ -214,6 +214,121 @@ Special Registers Altered:
     FX OX UX XX
     VXSNAN VXISI VXIMZ
 ```
+## Floating Twin Multiply-Add DCT
+
+**Add the following to Book I Section 4.6.6.3**
+
+X-Form
+
+```
+    |0     |6     |11      |16     |21      |31 |
+    | PO   |  FRT |  FRA   |  FRB  |   XO   |Rc |
+```
+
+* fdmadd FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+```
+    FRS <- FPADD64(FRT, FRB)
+    FRT <- FPMULADD64(FRT, FRA, FRB, 1, -1)
+```
+
+The Floating-Point operand in register FRT is added to the floating-point
+operand in register FRB and the result stored in FRS.
+
+Using the exact same operand input register values from FRT and FRB that
+were used to create FRS, the Floating-Point operand in register FRB
+is subtracted from the floating-point operand in register FRT and the
+result then multiplied by FRA to create an intermediate result that is
+stored in FRT.
+
+The add into FRS is treated exactly as `fadd`.  The creation
+of the result FRT is exact!y that of `fmsub`.  The creation of FRS and FRT are
+treated as parallel independent operations which occur at the same time.
+
+Note that if Rc=1 an Illegal Instruction is raised.
+Rc=1 is `RESERVED`
+
+Similar to `FRTp`, this instruction produces an implicit result,
+`FRS`, which under Scalar circumstances is defined as `FRT+1`.
+For SVP64 if `FRT` is a Vector, `FRS` begins immediately after the
+Vector `FRT` where the length of `FRT` is set by `SVSTATE.MAXVL`
+(Max Vector Length).
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+```
+
+## Floating Twin Multiply-Add FFT
+
+**Add the following to Book I Section 4.6.6.3**
+
+X-Form
+
+```
+    |0     |6     |11      |16     |21      |31 |
+    | PO   |  FRT |  FRA   |  FRB  |   XO   |Rc |
+```
+
+* ffmadd FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+```
+    FRS <- FPMULADD64(FRT, FRA, FRB, -1, 1)
+    FRT <- FPMULADD64(FRT, FRA, FRB, 1, 1)
+```
+
+The two operations
+
+```
+    FRS <- -([(FRT) * (FRA)] - (FRB))
+    FRT <-   [(FRT) * (FRA)] + (FRB)
+```
+
+are performed.
+
+The floating-point operand in register FRT is multiplied
+by the floating-point operand in register FRA. The float-
+ing-point operand in register FRB is added to
+this intermediate result, and the intermediate stored in FRS.
+
+Using the exact same values of FRT, FRT and FRB as used to create FRS,
+the floating-point operand in register FRT is multiplied
+by the floating-point operand in register FRA. The float-
+ing-point operand in register FRB is subtracted from
+this intermediate result, and the intermediate stored in FRT.
+
+FRT is created as if
+a `fmadd` operation had been performed. FRS is created as if
+a `fnmsub` operation had simultaneously been performed with
+the exact same register operands, in parallel, independently,
+at exactly the same time.
+
+FRT is a Read-Modify-Write operation.  
+
+Note that if Rc=1 an Illegal Instruction is raised.
+Rc=1 is `RESERVED`
+
+Similar to `FRTp`, this instruction produces an implicit result,
+`FRS`, which under Scalar circumstances is defined as `FRT+1`.
+For SVP64 if `FRT` is a Vector, `FRS` begins immediately after the
+Vector `FRT` where the length of `FRT` is set by `SVSTATE.MAXVL`
+(Max Vector Length).
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+```
+
 
 ## [DRAFT] Floating Add FFT/DCT [Single]