re PR target/86348 (ICE: in curr_insn_transform, at lra-constraints.c:3919: unable...

	PR target/86348
	* config/i386/sse.md (*vec_extractv4si_0_zext_sse4): Use
	alternative 0 in preferred_for_speed attribute.

testsuite/ChangeLog:

	PR target/86348
	* gcc.target/i386/pr86348.c: New test.

From-SVN: r262228

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1edab9e2be65ddd45af6caf7e83a22b171103d7f..09b24e65311d52f3612aee85c73c554f5cfb5ff6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-28  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/86348
+       * config/i386/sse.md (*vec_extractv4si_0_zext_sse4): Use
+       alternative 0 in preferred_for_speed attribute.
+
 2018-06-28  Paul Koning  <ni1d@arrl.net>
 
        * config/pdp11/pdp11-protos.h (pdp11_shift_length): New function.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 2d4e495890d93e81ba63e330609540eaca155890..0420da8035c7436af296693bca7b06354c344e8f 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13715,7 +13715,7 @@
   "#"
   [(set_attr "isa" "x64,*,avx512f")
    (set (attr "preferred_for_speed")
-     (cond [(eq_attr "alternative" "1")
+     (cond [(eq_attr "alternative" "0")
              (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
           ]
           (symbol_ref "true")))])

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b7a47ed979c39335f1f8dd13b9473afa2cb8019a..197a46833754738e99430f70c18cb92e15f4ae8c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-06-28  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/86348
+       * gcc.target/i386/pr86348.c: New test.
+
 2018-06-28  Wilco Dijkstra  <wdijkstr@arm.com>
 
        * gcc.target/aarch64/f16_mov_immediate_3.c: Fix testcase.

diff --git a/gcc/testsuite/gcc.target/i386/pr86348.c b/gcc/testsuite/gcc.target/i386/pr86348.c
new file mode 100644 (file)
index 0000000..c4a3c9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr86348.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O -mtune=athlon -msse4" } */
+
+int i;
+unsigned __attribute__ ((__vector_size__ (16))) v;
+
+void
+foo (void)
+{
+  v *= i;
+  i = i > -(long long) v[0];
+}