---------- Begin Simulation Statistics ----------
-host_inst_rate 69440 # Simulator instruction rate (inst/s)
-host_mem_usage 210892 # Number of bytes of host memory used
-host_seconds 1323.48 # Real time elapsed on the host
-host_tick_rate 76516395 # Simulator tick rate (ticks/s)
+host_inst_rate 55182 # Simulator instruction rate (inst/s)
+host_mem_usage 156168 # Number of bytes of host memory used
+host_seconds 1665.47 # Real time elapsed on the host
+host_tick_rate 59164617 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
-sim_seconds 0.101268 # Number of seconds simulated
-sim_ticks 101268061000 # Number of ticks simulated
+sim_seconds 0.098537 # Number of seconds simulated
+sim_ticks 98536744000 # Number of ticks simulated
system.cpu.AGEN-Unit.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.instReqsProcessed 91903057 # Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.predictedNotTaken 8198984 # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 2041701 # Number of Branches Predicted As Taken (True).
-system.cpu.Decode-Unit.instReqsProcessed 91903057 # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.instReqsProcessed 92657148 # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.predictedNotTaken 8232810 # Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 2041716 # Number of Branches Predicted As Taken (True).
+system.cpu.Decode-Unit.instReqsProcessed 92657148 # Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.cyclesExecuted 64907308 # Number of Cycles Execution Unit was used.
system.cpu.Execution-Unit.instReqsProcessed 64907696 # Number of Instructions Requests that completed in this resource.
system.cpu.Execution-Unit.predictedNotTakenIncorrect 3739118 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect 1029596 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
-system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed.
-system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
-system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed.
-system.cpu.Fetch-Seq-Unit.instReqsProcessed 189586934 # Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.utilization 0.329356 # Utilization of Execution Unit (cycles / totalCycles).
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 191370621 # Number of Instructions Requests that completed in this resource.
system.cpu.Graduation-Unit.instReqsProcessed 91903056 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed.
-system.cpu.RegFile-Manager.instReqsProcessed 188816950 # Number of Instructions Requests that completed in this resource.
+system.cpu.RegFile-Manager.instReqsProcessed 196152134 # Number of Instructions Requests that completed in this resource.
+system.cpu.activity 96.743392 # Percentage of cycles cpu is active
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
-system.cpu.cpi 2.203802 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 2.203802 # CPI: Total CPI of All Threads
+system.cpu.contextSwitches 1 # Number of context switches
+system.cpu.cpi 2.144363 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 2.144363 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51623.700624 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48550.526316 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19995717 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 24831000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 51569.473684 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48547.368421 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 24495500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 481 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 23061500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 23060000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56415.277031 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53415.277031 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56295.857988 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53295.857988 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 104876000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 104654000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 99299000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 99077000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11918.612686 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55430.341880 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52425.235647 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26494961 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 129707000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 55333.976007 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52329.477292 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 129149500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2340 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 122360500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 122137000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55430.341880 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52425.235647 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55333.976007 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52329.477292 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26494961 # number of overall hits
-system.cpu.dcache.overall_miss_latency 129707000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 26494967 # number of overall hits
+system.cpu.dcache.overall_miss_latency 129149500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2340 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 122360500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 2334 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 122137000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1441.819572 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26495076 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1441.684134 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.dcache_port.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource.
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
-system.cpu.icache.ReadReq_accesses 97683877 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 27282.787360 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 24026.266636 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 97675238 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 235696000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 98713473 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 27258.057090 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23994.339402 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 98704785 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 236818000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000088 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 8639 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 205809000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000088 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 8566 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_misses 8688 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 205583500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 8568 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 11402.666122 # Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles::no_targets 1000 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 11520.166317 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 1000 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 97683877 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 27282.787360 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 24026.266636 # average overall mshr miss latency
-system.cpu.icache.demand_hits 97675238 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 235696000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 98713473 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 27258.057090 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23994.339402 # average overall mshr miss latency
+system.cpu.icache.demand_hits 98704785 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 236818000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000088 # miss rate for demand accesses
-system.cpu.icache.demand_misses 8639 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 205809000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 8566 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_misses 8688 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 205583500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 8568 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 97683877 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 27282.787360 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 24026.266636 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 98713473 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 27258.057090 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23994.339402 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 97675238 # number of overall hits
-system.cpu.icache.overall_miss_latency 235696000 # number of overall miss cycles
+system.cpu.icache.overall_hits 98704785 # number of overall hits
+system.cpu.icache.overall_miss_latency 236818000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000088 # miss rate for overall accesses
-system.cpu.icache.overall_misses 8639 # number of overall misses
-system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 205809000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 8566 # number of overall MSHR misses
+system.cpu.icache.overall_misses 8688 # number of overall misses
+system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 205583500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 8568 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 6732 # number of replacements
-system.cpu.icache.sampled_refs 8566 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 6734 # number of replacements
+system.cpu.icache.sampled_refs 8568 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1428.614683 # Cycle average of tags in use
-system.cpu.icache.total_refs 97675238 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1428.229557 # Cycle average of tags in use
+system.cpu.icache.total_refs 98704785 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache_port.instReqsProcessed 97683876 # Number of Instructions Requests that completed in this resource.
-system.cpu.ipc 0.453761 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.453761 # IPC: Total IPC of All Threads
+system.cpu.icache_port.instReqsProcessed 98713472 # Number of Instructions Requests that completed in this resource.
+system.cpu.idleCycles 6417911 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.466339 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.466339 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 97683924 # ITB accesses
+system.cpu.itb.fetch_accesses 98713520 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 97683877 # ITB hits
+system.cpu.itb.fetch_hits 98713473 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52413.043478 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40003.432494 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 91618000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52296.624714 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 91414500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 69926000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 9041 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52240.613777 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40013.548808 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5978 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 160013000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.338790 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_accesses 9043 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52161.443030 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5980 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 159770500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.338715 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 122561500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338790 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338715 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52414.414414 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 5818000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52216.216216 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 5796000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.968317 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.968977 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 10789 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52303.263355 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40009.873207 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5978 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 251631000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.445917 # miss rate for demand accesses
+system.cpu.l2cache.demand_accesses 10791 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52210.559135 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5980 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 251185000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.445834 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 192487500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.445917 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_latency 192511500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.445834 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 10789 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52303.263355 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40009.873207 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 10791 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52210.559135 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5978 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 251631000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.445917 # miss rate for overall accesses
+system.cpu.l2cache.overall_hits 5980 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 251185000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.445834 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4811 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 192487500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.445917 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_latency 192511500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.445834 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2039.371088 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 5964 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2038.814805 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 5966 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 202536123 # number of cpu cycles simulated
+system.cpu.numCycles 197073489 # number of cpu cycles simulated
+system.cpu.runCycles 190655578 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
+system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.threadCycles 202536123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-0.idleCycles 98359969 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles 98713520 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization 50.089700 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 104416341 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 92657148 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 47.016546 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 103581004 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.runCycles 93492485 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-2.utilization 47.440417 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 170536358 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-3.utilization 13.465602 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 105170433 # Number of cycles 0 instructions are processed.
+system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-4.utilization 46.633901 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 197073489 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff