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display 64 bits of msr
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Nov 2021 19:07:46 +0000 (19:07 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Nov 2021 19:07:46 +0000 (19:07 +0000)
src/openpower/test/runner.py patch | blob | history

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index c429ee14bea49b69412444964773d42e67ac6cc0..f7ce218691e67a35f23742d2e719532b80d9f3b4 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -381,7 +381,7 @@ class TestRunnerBase(FHDLTestCase):
 
         traces += [('ld/st port interface', {'submodule': pi_module}, [
             'oper_r__insn_type',
-            'oper_r__msr',
+            'oper_r__msr[63:0]',
             'ldst_port0_is_ld_i',
             'ldst_port0_is_st_i',
             'ldst_port0_busy_o',