i965: Initial Ivybridge Clip state setup.

Copied from gen6_clip_state.c.

This enables early culling and sets the necessary fields.  Otherwise, it
is entirely the same, so I doubt this patch is strictly necessary for a
functional driver.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index dcecf3a741e424d3b0de1787887fe756d97dead7..c281320c2747e216254a881bf9773ad8769abb7f 100644 (file)
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -98,6 +98,7 @@ DRIVER_SOURCES = \
        gen6_vs_state.c \
        gen6_wm_state.c \
        gen7_cc_state.c \
+       gen7_clip_state.c \
        gen7_sf_state.c \
        gen7_urb.c \
        gen7_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 5e6f88a753009809a4abf92db3b71b9b4c4000b3..04d5863b8896657a36a37a548ef75c3c54bd3912 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -939,6 +939,15 @@
 
 #define _3DSTATE_CLIP                          0x7812 /* GEN6+ */
 /* DW1 */
+# define GEN7_CLIP_WINDING_CW                           (0 << 20)
+# define GEN7_CLIP_WINDING_CCW                          (1 << 20)
+# define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_8          (0 << 19)
+# define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_4          (1 << 19)
+# define GEN7_CLIP_EARLY_CULL                           (1 << 18)
+# define GEN7_CLIP_CULLMODE_BOTH                        (0 << 16)
+# define GEN7_CLIP_CULLMODE_NONE                        (1 << 16)
+# define GEN7_CLIP_CULLMODE_FRONT                       (2 << 16)
+# define GEN7_CLIP_CULLMODE_BACK                        (3 << 16)
 # define GEN6_CLIP_STATISTICS_ENABLE                   (1 << 10)
 /**
  * Just does cheap culling based on the clip distance.  Bits must be

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index e9af591c915cf449731088833edd6e2e035a0e79..ec680e4205e66f2cd98e3f3c2101e79b51c07fe7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -113,6 +113,7 @@ extern const struct brw_tracked_state gen6_wm_constants;
 extern const struct brw_tracked_state gen6_wm_state;
 extern const struct brw_tracked_state gen7_blend_state_pointer;
 extern const struct brw_tracked_state gen7_cc_state_pointer;
+extern const struct brw_tracked_state gen7_clip_state;
 extern const struct brw_tracked_state gen7_depth_stencil_state_pointer;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_sbe_state;

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 79a173d479082b4b9e6ec62c6a6ad7145c394d90..e3fd09110298681afb97c541d6134b64875e5ad4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -214,7 +214,7 @@ const struct brw_tracked_state *gen7_atoms[] =
 
    &gen6_vs_state,
    &gen6_gs_state,
-   &gen6_clip_state,
+   &gen7_clip_state,
    &gen7_sbe_state,
    &gen7_sf_state,
    &gen7_wm_state,

diff --git a/src/mesa/drivers/dri/i965/gen7_clip_state.c b/src/mesa/drivers/dri/i965/gen7_clip_state.c
new file mode 100644 (file)
index 0000000..c23ba8c
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen7_clip_state.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright © 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_clip_state(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &intel->ctx;
+   uint32_t depth_clamp = 0;
+   uint32_t provoking, userclip;
+   uint32_t dw1 = GEN6_CLIP_STATISTICS_ENABLE;
+
+   /* _NEW_BUFFERS */
+   GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+
+   dw1 |= GEN7_CLIP_EARLY_CULL;
+
+   /* _NEW_POLYGON */
+   if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
+      dw1 |= GEN7_CLIP_WINDING_CCW;
+
+   if (ctx->Polygon.CullFlag) {
+      switch (ctx->Polygon.CullFaceMode) {
+      case GL_FRONT:
+        dw1 |= GEN7_CLIP_CULLMODE_FRONT;
+        break;
+      case GL_BACK:
+        dw1 |= GEN7_CLIP_CULLMODE_BACK;
+        break;
+      case GL_FRONT_AND_BACK:
+        dw1 |= GEN7_CLIP_CULLMODE_BOTH;
+        break;
+      default:
+        assert(!"Should not get here: invalid CullFlag");
+        break;
+      }
+   } else {
+      dw1 |= GEN7_CLIP_CULLMODE_NONE;
+   }
+
+   /* _NEW_TRANSFORM */
+   if (!ctx->Transform.DepthClamp)
+      depth_clamp = GEN6_CLIP_Z_TEST;
+
+   /* _NEW_LIGHT */
+   if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
+      provoking =
+        (0 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
+        (1 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
+        (0 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
+   } else {
+      provoking =
+        (2 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
+        (2 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
+        (1 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
+   }
+
+   /* _NEW_TRANSFORM */
+   userclip = (1 << brw_count_bits(ctx->Transform.ClipPlanesEnabled)) - 1;
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
+   OUT_BATCH(dw1);
+   OUT_BATCH(GEN6_CLIP_ENABLE |
+            GEN6_CLIP_API_OGL |
+            GEN6_CLIP_MODE_NORMAL |
+            GEN6_CLIP_XY_TEST |
+            userclip << GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT |
+            depth_clamp |
+            provoking);
+   OUT_BATCH(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT |
+             U_FIXED(255.875, 3) << GEN6_CLIP_MAX_POINT_WIDTH_SHIFT |
+             GEN6_CLIP_FORCE_ZERO_RTAINDEX);
+   ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen7_clip_state = {
+   .dirty = {
+      .mesa  = (_NEW_BUFFERS |
+                _NEW_POLYGON |
+                _NEW_LIGHT |
+                _NEW_TRANSFORM),
+      .brw   = BRW_NEW_CONTEXT,
+      .cache = 0
+   },
+   .emit = upload_clip_state,
+};