Fix constants bound to single bit arguments (fixes #2383)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index fb6623f023844c4407b65cbe7ecd56a123255177..8cd459913c241b98a981860f46df0dfa68ec6ea6 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -3337,6 +3337,14 @@ skip_dynamic_range_lvalue_expansion:;
                                                wire->type = AST_LOCALPARAM;
                                                wire->attributes.erase(ID::nosync);
                                                wire->children.insert(wire->children.begin(), arg->clone());
+                                               // args without a range implicitly have width 1
+                                               if (wire->children.back()->type != AST_RANGE) {
+                                                       AstNode* range = new AstNode();
+                                                       range->type = AST_RANGE;
+                                                       wire->children.push_back(range);
+                                                       range->children.push_back(mkconst_int(0, true));
+                                                       range->children.push_back(mkconst_int(0, true));
+                                               }
                                                continue;
                                        }
                                        AstNode *wire_id = new AstNode(AST_IDENTIFIER);

diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v
index 3bfff4acd8dadb1e4e5dd25a0f930987647e459e..567bccc2542f1a06c17fc76c847a4a181d20c689 100644 (file)
--- a/tests/various/const_arg_loop.v
+++ b/tests/various/const_arg_loop.v
@@ -39,6 +39,12 @@ module top;
                end
        endfunction
 
+       function automatic [16:0] operation4;
+               input [15:0] a;
+               input b;
+               operation4 = {a, b};
+       endfunction
+
        wire [31:0] a;
        assign a = 2;
 
@@ -53,6 +59,9 @@ module top;
        wire [31:0] x3;
        assign x3 = operation3(A, a);
 
+       wire [16:0] x4;
+       assign x4 = operation4(a[15:0], 0);
+
 // `define VERIFY
 `ifdef VERIFY
     assert property (a == 2);
@@ -60,5 +69,6 @@ module top;
     assert property (x1 == 16);
     assert property (x2 == 4);
     assert property (x3 == 16);
+    assert property (x4 == a << 1);
 `endif
 endmodule