(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index aeb7b771871bfcb1b14b547d444227d5ce6d487f..82de8682dd79928477147e43f56618d67872caf6 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -149,6 +149,20 @@ Available options to combine:
 * `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
   `OR` of all tests, respectively.
 
+Pseudocode for Rc in sv.bc
+
+```
+# Use bit 30, disable AA
+Rc = AA
+AA = 0
+```
+
+Pseudocode for Rc in sv.bclr
+
+```
+Rc = instr[16]
+```
+
 Pseudocode for Horizontal-First Mode:
 
 ```