migen.fhdl.std -> migen

diff --git a/misoc/com/gpio.py b/misoc/com/gpio.py
index 88a49040bfc7e8c1c8029872d5e2a0fdbc0f67d0..6db225fbc40627d072d0c7c68d8ac888dd969016 100644 (file)
--- a/misoc/com/gpio.py
+++ b/misoc/com/gpio.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 

diff --git a/misoc/com/liteethmini/common.py b/misoc/com/liteethmini/common.py
index a5f0b3fc80839632ad11835cb49a4f1ba2f5bae7..21d0da08fa1838dbb083639fd626cd7d8798718b 100644 (file)
--- a/misoc/com/liteethmini/common.py
+++ b/misoc/com/liteethmini/common.py
@@ -1,7 +1,7 @@
 import math
 from collections import OrderedDict
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.record import *
 from migen.genlib.fsm import FSM, NextState

diff --git a/misoc/com/spi/__init__.py b/misoc/com/spi/__init__.py
index a78a6db41bab46e7eb907c4c29bb11121605f0dd..029a0beca6199223eb9b7ee5566fe91731936366 100644 (file)
--- a/misoc/com/spi/__init__.py
+++ b/misoc/com/spi/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.genlib.fsm import FSM, NextState
 

diff --git a/misoc/com/spi/test/spi_master_tb.py b/misoc/com/spi/test/spi_master_tb.py
index 51a30c66bc75260d219222ff8f017d5773a20862..e0febf5364c0309624a8e6692782183e24d87509 100644 (file)
--- a/misoc/com/spi/test/spi_master_tb.py
+++ b/misoc/com/spi/test/spi_master_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 

diff --git a/misoc/com/uart/__init__.py b/misoc/com/uart/__init__.py
index ffc39b48779eac5ca376dc6b096f1a18fe052ed9..bc00e5060864249fb7c7eb0f3904439ab789ee96 100644 (file)
--- a/misoc/com/uart/__init__.py
+++ b/misoc/com/uart/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.genlib.record import Record

diff --git a/misoc/com/uart/bridge.py b/misoc/com/uart/bridge.py
index 6917f35559be406d7e708b1ae256ea90d23ea6b4..61cc098b679f69000e3130245dc0bb8dc0e74f84 100644 (file)
--- a/misoc/com/uart/bridge.py
+++ b/misoc/com/uart/bridge.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.tools.wishbone import WishboneStreamingBridge
 from misoc.com.uart.phy.serial import UARTPHYSerial

diff --git a/misoc/com/uart/phy/serial.py b/misoc/com/uart/phy/serial.py
index 747dbd21749968cbaca54c361f3cfc2f18372f9a..6458d4e33043a554c41d573bd98697a51a8a76ca 100644 (file)
--- a/misoc/com/uart/phy/serial.py
+++ b/misoc/com/uart/phy/serial.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.flow.actor import Sink, Source

diff --git a/misoc/com/uart/phy/sim.py b/misoc/com/uart/phy/sim.py
index a7348e0bf441ac263ed2b9c0cf59d83b37e7625e..85a215d5fcabe40852427570abc6a05d35aeba06 100644 (file)
--- a/misoc/com/uart/phy/sim.py
+++ b/misoc/com/uart/phy/sim.py
@@ -2,7 +2,7 @@ import os
 import pty
 import time
 
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import Sink, Source
 
 

diff --git a/misoc/cpu/identifier.py b/misoc/cpu/identifier.py
index 7f24c6124a980b0c9820e531b3d705e19fdb52a1..a70f44b05d338a0e44c53631197cb7b2537b952e 100644 (file)
--- a/misoc/cpu/identifier.py
+++ b/misoc/cpu/identifier.py
@@ -1,6 +1,6 @@
 import subprocess
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 def get_id():

diff --git a/misoc/cpu/lm32.py b/misoc/cpu/lm32.py
index 8ea7637b2d7b70d0cd6e6ac8b3bcfa005696268b..ca9b001cd921309d81998b82f495392972bc6f12 100644 (file)
--- a/misoc/cpu/lm32.py
+++ b/misoc/cpu/lm32.py
@@ -1,6 +1,6 @@
 import os
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 
 

diff --git a/misoc/cpu/mor1kx.py b/misoc/cpu/mor1kx.py
index 1169aba730f116303c5359f473db70bd0d35ee7d..f9c696420b27ddb37ed144a91b78fe99c815bdc2 100644 (file)
--- a/misoc/cpu/mor1kx.py
+++ b/misoc/cpu/mor1kx.py
@@ -1,6 +1,6 @@
 import os
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 
 

diff --git a/misoc/cpu/timer.py b/misoc/cpu/timer.py
index 4061f837095f9467c86223391e6b78982d8b6fd6..62a88acf10ec97978018937a55b63ada5e410b5d 100644 (file)
--- a/misoc/cpu/timer.py
+++ b/misoc/cpu/timer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 

diff --git a/misoc/mem/flash/norflash16.py b/misoc/mem/flash/norflash16.py
index 42c68c07d4b86f6e81d30105b22ea2690b112b4d..2649a4ae71fbee256499d1980d500a935b9f39f2 100644 (file)
--- a/misoc/mem/flash/norflash16.py
+++ b/misoc/mem/flash/norflash16.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 

diff --git a/misoc/mem/flash/spiflash.py b/misoc/mem/flash/spiflash.py
index 1e099a75eb74484ce4051d403160a2520ead29cc..b63840c57c83172a04e768a6d790a90c40144566 100644 (file)
--- a/misoc/mem/flash/spiflash.py
+++ b/misoc/mem/flash/spiflash.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.bus import wishbone
 from migen.genlib.misc import timeline

diff --git a/misoc/mem/sdram/core/__init__.py b/misoc/mem/sdram/core/__init__.py
index 287bdf57d4abfb44b505ade5c33c79c601d5488f..6d7057f1bd2154e2d9c8ab42d1af90be647c4d04 100644 (file)
--- a/misoc/mem/sdram/core/__init__.py
+++ b/misoc/mem/sdram/core/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.bank.description import *
 

diff --git a/misoc/mem/sdram/core/lasmibus.py b/misoc/mem/sdram/core/lasmibus.py
index c1d3b0cde371da0e451d41917ced690d177e0e15..acdb3702ecffdca9bd2f53820a3fb3a827d0a832 100644 (file)
--- a/misoc/mem/sdram/core/lasmibus.py
+++ b/misoc/mem/sdram/core/lasmibus.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *

diff --git a/misoc/mem/sdram/core/lasmicon/__init__.py b/misoc/mem/sdram/core/lasmicon/__init__.py
index 170e085ae28c2d23d3b91d1af90097fbc7d93c91..e06a167d76fa3f0c85acd87cacdf34455f57ed6b 100644 (file)
--- a/misoc/mem/sdram/core/lasmicon/__init__.py
+++ b/misoc/mem/sdram/core/lasmicon/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.mem.sdram.phy import dfi
 from misoc.mem.sdram.core import lasmibus

diff --git a/misoc/mem/sdram/core/lasmicon/bankmachine.py b/misoc/mem/sdram/core/lasmicon/bankmachine.py
index 1f58dd4358d0a110b800dee0c82db1af2f9220b8..4e3cbd65747e9738b20100c2cb794c1f238e7a2b 100644 (file)
--- a/misoc/mem/sdram/core/lasmicon/bankmachine.py
+++ b/misoc/mem/sdram/core/lasmicon/bankmachine.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.roundrobin import *
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree

diff --git a/misoc/mem/sdram/core/lasmicon/multiplexer.py b/misoc/mem/sdram/core/lasmicon/multiplexer.py
index d03d4dfda24335633c9542482ed09a65d2e0eec2..150fe1ccc315cfc38f0465e8fe3e38983373f101 100644 (file)
--- a/misoc/mem/sdram/core/lasmicon/multiplexer.py
+++ b/misoc/mem/sdram/core/lasmicon/multiplexer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.roundrobin import *
 from migen.genlib.misc import optree
 from migen.genlib.fsm import FSM, NextState

diff --git a/misoc/mem/sdram/core/lasmicon/perf.py b/misoc/mem/sdram/core/lasmicon/perf.py
index 2c7e8cf0a540c04aab3c21f9014a1fcbd80dab51..2283adc09ee37cafd2466fe25fe95a3c13fd2a0c 100644 (file)
--- a/misoc/mem/sdram/core/lasmicon/perf.py
+++ b/misoc/mem/sdram/core/lasmicon/perf.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 

diff --git a/misoc/mem/sdram/core/lasmicon/refresher.py b/misoc/mem/sdram/core/lasmicon/refresher.py
index 12aeefc4ee2c149280c86f3109203804105acf07..8af685fc0ef34a4cd7f2865fa8761be9fd88285f 100644 (file)
--- a/misoc/mem/sdram/core/lasmicon/refresher.py
+++ b/misoc/mem/sdram/core/lasmicon/refresher.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import timeline
 from migen.genlib.fsm import FSM
 

diff --git a/misoc/mem/sdram/core/lasmixbar.py b/misoc/mem/sdram/core/lasmixbar.py
index cbba9499c1d07e3abb01007a7d34a1730a3d8567..1af682ec39e6e158002cdbefddbd718d52f32a7b 100644 (file)
--- a/misoc/mem/sdram/core/lasmixbar.py
+++ b/misoc/mem/sdram/core/lasmixbar.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *
 from migen.genlib.misc import optree

diff --git a/misoc/mem/sdram/core/minicon/__init__.py b/misoc/mem/sdram/core/minicon/__init__.py
index dd70f58cf66580c527595e7365a01f9688b54d17..dcb48e5dd399e0d65f320d53127be558979054f9 100644 (file)
--- a/misoc/mem/sdram/core/minicon/__init__.py
+++ b/misoc/mem/sdram/core/minicon/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree, WaitTimer

diff --git a/misoc/mem/sdram/frontend/dma_lasmi.py b/misoc/mem/sdram/frontend/dma_lasmi.py
index 54c4843359b5f769c65bf066ebcd66f4160974ca..b505b3ed65b4f774246bf8caa31011ac8b7b83cc 100644 (file)
--- a/misoc/mem/sdram/frontend/dma_lasmi.py
+++ b/misoc/mem/sdram/frontend/dma_lasmi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import *
 from migen.genlib.fifo import SyncFIFO
 

diff --git a/misoc/mem/sdram/frontend/memtest.py b/misoc/mem/sdram/frontend/memtest.py
index 9b3c62a3de089bd59e26609ec0fba0313bd1b247..58d56233e7490368ea7a18dc34efe2e7f9605998 100644 (file)
--- a/misoc/mem/sdram/frontend/memtest.py
+++ b/misoc/mem/sdram/frontend/memtest.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import optree
 from migen.bank.description import *
 from migen.actorlib.spi import *

diff --git a/misoc/mem/sdram/frontend/wishbone2lasmi.py b/misoc/mem/sdram/frontend/wishbone2lasmi.py
index 9524734a9974cc937a3d40ef091f229a5eaed0b7..d1dfd1bcc3d680e48e686a965a79c0617194446e 100644 (file)
--- a/misoc/mem/sdram/frontend/wishbone2lasmi.py
+++ b/misoc/mem/sdram/frontend/wishbone2lasmi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import FSM, NextState
 
 class WB2LASMI(Module):

diff --git a/misoc/mem/sdram/module.py b/misoc/mem/sdram/module.py
index f15867d8edb01be67b1a4ac305819c7bed668237..bf1ce74fc01594c8826685fca3b2a59430358468 100644 (file)
--- a/misoc/mem/sdram/module.py
+++ b/misoc/mem/sdram/module.py
@@ -16,7 +16,7 @@
 
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 from misoc.mem import sdram
 
 

diff --git a/misoc/mem/sdram/phy/dfi.py b/misoc/mem/sdram/phy/dfi.py
index 76379e283fd6a518eb92ce54c80b4ddfd5dff1ba..aae56b0d380075f0403fa0f2bbd7bb90f333e7ae 100644 (file)
--- a/misoc/mem/sdram/phy/dfi.py
+++ b/misoc/mem/sdram/phy/dfi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 
 

diff --git a/misoc/mem/sdram/phy/dfii.py b/misoc/mem/sdram/phy/dfii.py
index ffbdc7dd35cd95f35436703a0343f30f531de91c..b79b8d941cc96ec75aa580965dd6ef1514cefe41 100644 (file)
--- a/misoc/mem/sdram/phy/dfii.py
+++ b/misoc/mem/sdram/phy/dfii.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 from misoc.mem.sdram.phy import dfi

diff --git a/misoc/mem/sdram/phy/gensdrphy.py b/misoc/mem/sdram/phy/gensdrphy.py
index 80c589d64f56f650472c4e30b52f4bc3e615e340..a349cdf5e688be7a1acaa74afb3d0731a9671d01 100644 (file)
--- a/misoc/mem/sdram/phy/gensdrphy.py
+++ b/misoc/mem/sdram/phy/gensdrphy.py
@@ -21,7 +21,7 @@
 # This PHY only supports CAS Latency 2.
 #
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.fhdl.specials import *
 

diff --git a/misoc/mem/sdram/phy/initsequence.py b/misoc/mem/sdram/phy/initsequence.py
index 3bdf5f3af7f633cf084c15a8aa4bc886998d6c3c..8ca1db005f8b5397e090e500c2126eef01600234 100644 (file)
--- a/misoc/mem/sdram/phy/initsequence.py
+++ b/misoc/mem/sdram/phy/initsequence.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import log2_int
+from migen import log2_int
 
 
 def get_sdram_phy_header(sdram_phy_settings):

diff --git a/misoc/mem/sdram/phy/k7ddrphy.py b/misoc/mem/sdram/phy/k7ddrphy.py
index 5a2e0fc9330654e1a003fe6f3e1717fed6bdfe8e..044a7123f6465d7bbbcf21e2e90ac41a63ae8116 100644 (file)
--- a/misoc/mem/sdram/phy/k7ddrphy.py
+++ b/misoc/mem/sdram/phy/k7ddrphy.py
@@ -1,6 +1,6 @@
 # tCK=5ns CL=7 CWL=6
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 from misoc.mem.sdram.phy.dfi import *

diff --git a/misoc/mem/sdram/phy/s6ddrphy.py b/misoc/mem/sdram/phy/s6ddrphy.py
index 7153f05c0677b51024f59f0947833d860be896c1..c2f7e12eb7f9f591aa662366ebb9192b30544049 100644 (file)
--- a/misoc/mem/sdram/phy/s6ddrphy.py
+++ b/misoc/mem/sdram/phy/s6ddrphy.py
@@ -16,7 +16,7 @@
 # Write commands must be sent on phase 1.
 #
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 
 from misoc.mem.sdram.phy.dfi import *

diff --git a/misoc/mem/sdram/phy/simphy.py b/misoc/mem/sdram/phy/simphy.py
index 0588d082c4d66ec2ca22cdd1a73debccec32eff3..6b8bcf1929f65ecde5a9abea96c0e03a86b061b6 100644 (file)
--- a/misoc/mem/sdram/phy/simphy.py
+++ b/misoc/mem/sdram/phy/simphy.py
@@ -6,7 +6,7 @@
 # TODO:
 # - add $display support to Migen and manage timing violations?
 
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import *
 from misoc.mem.sdram.phy.dfi import *
 from misoc.mem import sdram

diff --git a/misoc/mem/sdram/test/abstract_transactions_lasmi.py b/misoc/mem/sdram/test/abstract_transactions_lasmi.py
index fd027f759b319145e59c65f848ab500d30cfc839..18d77963a575376d51908af842f219ab195f6635 100644 (file)
--- a/misoc/mem/sdram/test/abstract_transactions_lasmi.py
+++ b/misoc/mem/sdram/test/abstract_transactions_lasmi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 

diff --git a/misoc/mem/sdram/test/bankmachine_tb.py b/misoc/mem/sdram/test/bankmachine_tb.py
index 54578dcecd35e0ea5d7efd1bdeef2e3333106984..020d1268531a84722a964ef8f3b9c1b62e96c9c6 100644 (file)
--- a/misoc/mem/sdram/test/bankmachine_tb.py
+++ b/misoc/mem/sdram/test/bankmachine_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.code import lasmibus

diff --git a/misoc/mem/sdram/test/common.py b/misoc/mem/sdram/test/common.py
index 6c1c09ddbaedd6e79a087fc65b65e7f36d31bec7..8a537484e457cfc3a036c603a9543738a1315d42 100644 (file)
--- a/misoc/mem/sdram/test/common.py
+++ b/misoc/mem/sdram/test/common.py
@@ -1,7 +1,7 @@
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 
 from misoc import sdram
 

diff --git a/misoc/mem/sdram/test/lasmicon_df_tb.py b/misoc/mem/sdram/test/lasmicon_df_tb.py
index bee4a7d4032fccd23476dab66b12616290d73219..326d56a179da819daf30e4f806921003737cca13 100644 (file)
--- a/misoc/mem/sdram/test/lasmicon_df_tb.py
+++ b/misoc/mem/sdram/test/lasmicon_df_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core import lasmibus

diff --git a/misoc/mem/sdram/test/lasmicon_tb.py b/misoc/mem/sdram/test/lasmicon_tb.py
index 957e3e71ec23dce617d9dea6e36a70f9c264d4ff..469f8eb8fa05b7f55cd0a194811a599618346b26 100644 (file)
--- a/misoc/mem/sdram/test/lasmicon_tb.py
+++ b/misoc/mem/sdram/test/lasmicon_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core import lasmibus

diff --git a/misoc/mem/sdram/test/lasmicon_wb.py b/misoc/mem/sdram/test/lasmicon_wb.py
index 425bdf71fd6188a593dfcc65c6917d043a16a530..37c5b031ae26974e579f42ca0306aead3790d773 100644 (file)
--- a/misoc/mem/sdram/test/lasmicon_wb.py
+++ b/misoc/mem/sdram/test/lasmicon_wb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation

diff --git a/misoc/mem/sdram/test/minicon_tb.py b/misoc/mem/sdram/test/minicon_tb.py
index 8aa4f8997a8fce46c1407f8ef22927a4cf0c729c..8468d5f2d5cd627b8ac236eb6d21e76795df5eb4 100644 (file)
--- a/misoc/mem/sdram/test/minicon_tb.py
+++ b/misoc/mem/sdram/test/minicon_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import TRead, TWrite
 from migen.bus import wishbone
 from migen.sim.generic import Simulator

diff --git a/misoc/mem/sdram/test/refresher.py b/misoc/mem/sdram/test/refresher.py
index 4a13c19e3f3c6745e7a30305a64f93a2747a4d26..5722b09dd3377939403d3a5a49edd626d5bd1e7c 100644 (file)
--- a/misoc/mem/sdram/test/refresher.py
+++ b/misoc/mem/sdram/test/refresher.py
@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core.lasmicon.refresher import *

diff --git a/misoc/soc/__init__.py b/misoc/soc/__init__.py
index 889be51dad48c759f79d733996164a55eb91c888..c114dbb17afa8a722ee4a5d8171d4be9ccf5d4dd 100644 (file)
--- a/misoc/soc/__init__.py
+++ b/misoc/soc/__init__.py
@@ -1,6 +1,6 @@
 from operator import itemgetter
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank import csrgen
 from migen.bus import wishbone, csr, wishbone2csr
 

diff --git a/misoc/soc/cpuif.py b/misoc/soc/cpuif.py
index ac812d518939340332dadd84a5877519f08f0f34..3ed2dd6d91a512944b284dd873770337458c0328 100644 (file)
--- a/misoc/soc/cpuif.py
+++ b/misoc/soc/cpuif.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import CSRStatus
 
 

diff --git a/misoc/soc/sdram.py b/misoc/soc/sdram.py
index d46beb1cc4a70caaf41d86ca49eb28a3652bf950..e8d86a70e8b08f15e8d5bf2e69067e440e6247fe 100644 (file)
--- a/misoc/soc/sdram.py
+++ b/misoc/soc/sdram.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.record import *
 

diff --git a/misoc/tools/wishbone.py b/misoc/tools/wishbone.py
index 5b712bf8f9fd9f65d89692b8de8cc7b73a11a2f5..99b4c43e3fe06161ce9f82c616fd35912b1b8349 100644 (file)
--- a/misoc/tools/wishbone.py
+++ b/misoc/tools/wishbone.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.misc import chooser, Counter, WaitTimer
 from migen.genlib.record import Record

diff --git a/misoc/video/dvisampler/__init__.py b/misoc/video/dvisampler/__init__.py
index 1670ccfa7de8fb85bd77c2907280284df2da0677..fad0f9da1c687fbd4dde444e0fbd9b1dd845730a 100644 (file)
--- a/misoc/video/dvisampler/__init__.py
+++ b/misoc/video/dvisampler/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import AutoCSR
 
 from misoc.video.dvisampler.edid import EDID

diff --git a/misoc/video/dvisampler/analysis.py b/misoc/video/dvisampler/analysis.py
index 77003c7277f7ea034975928f8dd659d2c61bc796..189413fea9d1da592750c8139cbd0f3c4c73d9cc 100644 (file)
--- a/misoc/video/dvisampler/analysis.py
+++ b/misoc/video/dvisampler/analysis.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import Record

diff --git a/misoc/video/dvisampler/chansync.py b/misoc/video/dvisampler/chansync.py
index b83b8188d8626c043ddbdcf58ee647cbefbfedd1..3bd3fdba5ede39b63e981447cdbc663913ecd512 100644 (file)
--- a/misoc/video/dvisampler/chansync.py
+++ b/misoc/video/dvisampler/chansync.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import _inc
 from migen.genlib.record import Record, layout_len

diff --git a/misoc/video/dvisampler/charsync.py b/misoc/video/dvisampler/charsync.py
index 102da27d7e2d2ccef4e0bd635435cf804b302017..93b0e556f9814554ea92a80d094004518f532701 100644 (file)
--- a/misoc/video/dvisampler/charsync.py
+++ b/misoc/video/dvisampler/charsync.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import optree
 from migen.bank.description import *

diff --git a/misoc/video/dvisampler/clocking.py b/misoc/video/dvisampler/clocking.py
index d13b1fb9d15b3952c115380706e591ec46425b7a..0fc8969b4f1af6dee49d13e48a629a96bf2062a0 100644 (file)
--- a/misoc/video/dvisampler/clocking.py
+++ b/misoc/video/dvisampler/clocking.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 

diff --git a/misoc/video/dvisampler/datacapture.py b/misoc/video/dvisampler/datacapture.py
index 8e91ad04acc868cacc27980acba0169edb54d891..49f0ccefbaef65f89285e8372d2fbf659f416fc7 100644 (file)
--- a/misoc/video/dvisampler/datacapture.py
+++ b/misoc/video/dvisampler/datacapture.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.bank.description import *
 

diff --git a/misoc/video/dvisampler/debug.py b/misoc/video/dvisampler/debug.py
index 67af06e6ef7bc07bcf49c4cb373bfa50c3d6234f..9e561383c3d28ad334ad1a6fdab43c052dd78251 100644 (file)
--- a/misoc/video/dvisampler/debug.py
+++ b/misoc/video/dvisampler/debug.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR

diff --git a/misoc/video/dvisampler/decoding.py b/misoc/video/dvisampler/decoding.py
index 2d0ddbf437161ca0d82bbe5044654bc57087ee97..fd8c0c6148966a543f930372f5a90cc6d9b77a4f 100644 (file)
--- a/misoc/video/dvisampler/decoding.py
+++ b/misoc/video/dvisampler/decoding.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import Record
 
 from misoc.video.dvisampler.common import control_tokens, channel_layout

diff --git a/misoc/video/dvisampler/dma.py b/misoc/video/dvisampler/dma.py
index 75458df746a5af8676ad305650d2b540e509b39a..7ed4f82974fef6f394d2d4d7245238d837df1256 100644 (file)
--- a/misoc/video/dvisampler/dma.py
+++ b/misoc/video/dvisampler/dma.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import FSM, NextState
 from migen.bank.description import *
 from migen.bank.eventmanager import *

diff --git a/misoc/video/dvisampler/edid.py b/misoc/video/dvisampler/edid.py
index 2a8e8b0828ee84cfcda36e9e64cf03bc773dd025..eb674b3ec1c0fb9d8a581302306fb48bc7ec7f2b 100644 (file)
--- a/misoc/video/dvisampler/edid.py
+++ b/misoc/video/dvisampler/edid.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM, NextState

diff --git a/misoc/video/dvisampler/wer.py b/misoc/video/dvisampler/wer.py
index 310e6d48dbf61dc2680e05d4730b40b43d59d55a..39d20289f115e6ec8205cc7a77000581012ed159 100644 (file)
--- a/misoc/video/dvisampler/wer.py
+++ b/misoc/video/dvisampler/wer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer

diff --git a/misoc/video/framebuffer/__init__.py b/misoc/video/framebuffer/__init__.py
index eec9404bae4da0e7d93043efd2106ec5a2a16a63..5071c943a538b2c65fa6dbd7d50da626411f4e0f 100644 (file)
--- a/misoc/video/framebuffer/__init__.py
+++ b/misoc/video/framebuffer/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.network import *
 from migen.flow import plumbing
 from migen.bank.description import AutoCSR

diff --git a/misoc/video/framebuffer/dvi.py b/misoc/video/framebuffer/dvi.py
index 0ba8b4b489c2591526f99c3bad6a4dbfe49850e5..03bb6acdf87ae91626689f9c122b48a93971ac01 100644 (file)
--- a/misoc/video/framebuffer/dvi.py
+++ b/misoc/video/framebuffer/dvi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import optree
 
 control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]

diff --git a/misoc/video/framebuffer/format.py b/misoc/video/framebuffer/format.py
index e3a3931f2931bbf847fb5dc3ce8a0a5da22e442d..210ec5ce19bd91225fd6a0985b40ab1dea709c01 100644 (file)
--- a/misoc/video/framebuffer/format.py
+++ b/misoc/video/framebuffer/format.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import *
 from migen.bank.description import CSRStorage
 from migen.genlib.record import Record

diff --git a/misoc/video/framebuffer/phy.py b/misoc/video/framebuffer/phy.py
index d77426c5561d187b7c1cee617be9234c02ea0889..2bb128fb7db8bdbfeab9740966811b778553ca09 100644 (file)
--- a/misoc/video/framebuffer/phy.py
+++ b/misoc/video/framebuffer/phy.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *

diff --git a/targets/de0nano.py b/targets/de0nano.py
index d823b0a67879089fb12a6de4f14406a990fe2b69..4664123609cdde8eb527a0b5d77a58d483e80134 100644 (file)
--- a/targets/de0nano.py
+++ b/targets/de0nano.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.mem.sdram.module import IS42S16160
 from misoc.mem.sdram.phy import gensdrphy

diff --git a/targets/kc705.py b/targets/kc705.py
index e9cf70e48aadfeb600f31881420118d26886bc2f..d85e98ec723beeccd8a836e4c51751e5d404755d 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT8JTF12864

diff --git a/targets/minispartan6.py b/targets/minispartan6.py
index ff5e4b8271d5761db82cb4961d5f171126c02b10..9c19122ca01d1d1124b31bee91cd4f26b74c5dae 100644 (file)
--- a/targets/minispartan6.py
+++ b/targets/minispartan6.py
@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.actorlib.fifo import SyncFIFO
 

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index fcd8481c4a6bbee5c66e00adc8754110485bf0fb..d71f61731fbff7fe3435e636d2db08e9a75cda48 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -2,7 +2,7 @@ import os
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 from mibuild.generic_platform import ConstraintError
 
 from misoc.mem.sdram.module import MT46V32M16

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 668be1de057b2f8635cdd8213a5da48ee546a633..c1ca91d12041df958029b47089de9f935a97428c 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT46H32M16

diff --git a/targets/ppro.py b/targets/ppro.py
index 1b5f43bf0e8357f20e3da75d59b3a62ee8663771..c4cb89e54b5d26842e84e0d9e460e96e9cabc7f5 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT48LC4M16

diff --git a/targets/simple.py b/targets/simple.py
index b28d5917fb31776443b2394e112cc08acf33249e..0c987d8eae77b194f6020c743df2af4fed39636f 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.io import CRG
 

diff --git a/targets/versa.py b/targets/versa.py
index fd787476a4c0edfd833c47bd8594beb304c28dfd..237df136ecd2e957b351bde9cc04a7ed20b11fa4 100644 (file)
--- a/targets/versa.py
+++ b/targets/versa.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.io import CRG