radv: Set correct registers for merged shader rings.

We need different regs to end up in s0/s1.

Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index b9cd6768c686b4cd9785e0f6ae4b247330f9bac9..7f306db5c487b944afb3c45b617f8fec4ce78894 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1580,19 +1580,31 @@ radv_get_preamble_cs(struct radv_queue *queue,
                }
 
                if (descriptor_bo) {
-                       uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
-                                          R_00B130_SPI_SHADER_USER_DATA_VS_0,
-                                          R_00B230_SPI_SHADER_USER_DATA_GS_0,
-                                          R_00B330_SPI_SHADER_USER_DATA_ES_0,
-                                          R_00B430_SPI_SHADER_USER_DATA_HS_0,
-                                          R_00B530_SPI_SHADER_USER_DATA_LS_0};
-
                        uint64_t va = radv_buffer_get_va(descriptor_bo);
-
-                       for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-                               radeon_set_sh_reg_seq(cs, regs[i], 2);
-                               radeon_emit(cs, va);
-                               radeon_emit(cs, va >> 32);
+                       if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
+                               uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
+                                               R_00B130_SPI_SHADER_USER_DATA_VS_0,
+                                               R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
+                                               R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
+
+                               for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
+                                       radeon_set_sh_reg_seq(cs, regs[i], 2);
+                                       radeon_emit(cs, va);
+                                       radeon_emit(cs, va >> 32);
+                               }
+                       } else {
+                               uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
+                                               R_00B130_SPI_SHADER_USER_DATA_VS_0,
+                                               R_00B230_SPI_SHADER_USER_DATA_GS_0,
+                                               R_00B330_SPI_SHADER_USER_DATA_ES_0,
+                                               R_00B430_SPI_SHADER_USER_DATA_HS_0,
+                                               R_00B530_SPI_SHADER_USER_DATA_LS_0};
+
+                               for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
+                                       radeon_set_sh_reg_seq(cs, regs[i], 2);
+                                       radeon_emit(cs, va);
+                                       radeon_emit(cs, va >> 32);
+                               }
                        }
                }