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add debug on zeroing-predication c.mv
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 3 Nov 2018 08:01:58 +0000
(08:01 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 3 Nov 2018 08:01:58 +0000
(08:01 +0000)
riscv/insn_template_sv.cc
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diff --git
a/riscv/insn_template_sv.cc
b/riscv/insn_template_sv.cc
index 1b3ca4f39087b2fdd8fd7e130e35826200119d96..d235ce3bbaa55b02319b5c08e97304381966c97e 100644
(file)
--- a/
riscv/insn_template_sv.cc
+++ b/
riscv/insn_template_sv.cc
@@
-230,6
+230,13
@@
reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
#ifndef INSN_TYPE_C_STACK_ST // XXX TODO: stack-based DEST_REG
reg_spec_t rdr = insn._DEST_REG();
bool dest_predicated = (dest_pred & (1<<*dest_offs)) != 0;
+#ifdef INSN_C_MV
+ fprintf(stderr, "post %s %x doffs %lx dp %x zeroing %d tozero %d" \
+ " rdr %d v %x\n",
+ xstr(INSN), INSNCODE,
+ dest_pred, *dest_offs, zeroing, dest_predicated,
+ rdr.reg, READ_REG(rdr));
+#endif
// don't check inversion here as dest_pred has already been inverted
if (zeroing && (!dest_predicated))
{