ARM: Don't always update CPSR.

diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index a154cac606788a34ed33a9655205c4b265a90619..41fd0552c63bb0e0e8c12a9dbfd9c036558df90a 100644 (file)
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -354,7 +354,8 @@ def template StoreCompleteAcc {{
     {
         Fault fault = NoFault;
 
-        %(op_dest_decl)s;
+        %(op_decl)s;
+        %(op_rd)s;
 
         if (%(predicate_test)s)
         {

diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa
index 5caab642c02e1298e1e190718ba132a43cff9aa1..ac2e077bad16d05a747f61ebff02e6173ac2cc8f 100644 (file)
--- a/src/arch/arm/isa/formats/util.isa
+++ b/src/arch/arm/isa/formats/util.isa
@@ -35,7 +35,6 @@ def ArmGenericCodeSubs(code):
     # Substitute in the shifted portion of operations
     new_code = re.sub(r'Rm_Imm', 'shift_rm_imm(Rm, shift_size, shift, Cpsr<29:>)', code)
     new_code = re.sub(r'Rm_Rs', 'shift_rm_rs(Rm, Rs, shift, Cpsr<29:>)', new_code)
-    new_code = re.sub(r'^', 'Cpsr = Cpsr;', new_code)
     return new_code
 
 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,