--- /dev/null
+# Copyright (c) 2015 ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+CPP?=cpp
+DTC?=dtc
+
+DTC_CPP_FLAGS=-nostdinc -undef
+
+TARGETS=\
+ armv7_gem5_v1_1cpu.dtb armv7_gem5_v1_2cpu.dtb \
+ armv7_gem5_v1_4cpu.dtb armv7_gem5_v1_8cpu.dtb \
+ armv7_gem5_v1_16cpu.dtb \
+ armv8_gem5_v1_1cpu.dtb armv8_gem5_v1_2cpu.dtb \
+ armv8_gem5_v1_4cpu.dtb armv8_gem5_v1_8cpu.dtb \
+ armv8_gem5_v1_16cpu.dtb
+
+GEN_DTS=mkdir -p .gen; \
+ $(CPP) -x assembler-with-cpp \
+ $(DTC_CPP_FLAGS) \
+ -DCONF_PLATFORM=\"platforms/$(1)\" \
+ -DCONF_CPUS=$(2) \
+ -o $@ $<
+
+all: $(TARGETS)
+
+.gen/armv7_gem5_v1_%cpu.dts: armv7.dts platforms/vexpress_gem5_v1.dtsi
+ $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+
+.gen/armv8_gem5_v1_%cpu.dts: armv8.dts platforms/vexpress_gem5_v1.dtsi
+ $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+
+%.dtb: .gen/%.dts
+ $(DTC) -I dts -O dtb -o $@ $<
+
+
+clean:
+ $(RM) -r .gen
+ $(RM) *.dtb
--- /dev/null
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+/dts-v1/;
+
+#include CONF_PLATFORM
+
+#define CPU(n) \
+ cpu@ ## n { \
+ device_type = "cpu"; \
+ compatible = "gem5,arm", "arm,cortex-a15"; \
+ reg = < n >; \
+ };
+
+/ {
+ model = "V2P-CA15";
+ compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0x4 0x00000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ #if CONF_CPUS > 0
+ CPU(0)
+ #endif
+ #if CONF_CPUS > 1
+ CPU(1)
+ #endif
+ #if CONF_CPUS > 2
+ CPU(2)
+ #endif
+ #if CONF_CPUS > 3
+ CPU(3)
+ #endif
+ #if CONF_CPUS > 4
+ CPU(4)
+ #endif
+ #if CONF_CPUS > 5
+ CPU(5)
+ #endif
+ #if CONF_CPUS > 6
+ CPU(6)
+ #endif
+ #if CONF_CPUS > 7
+ CPU(7)
+ #endif
+ #if CONF_CPUS > 8
+ CPU(8)
+ #endif
+ #if CONF_CPUS > 9
+ CPU(9)
+ #endif
+ #if CONF_CPUS > 10
+ CPU(10)
+ #endif
+ #if CONF_CPUS > 11
+ CPU(11)
+ #endif
+ #if CONF_CPUS > 12
+ CPU(12)
+ #endif
+ #if CONF_CPUS > 13
+ CPU(13)
+ #endif
+ #if CONF_CPUS > 14
+ CPU(14)
+ #endif
+ #if CONF_CPUS > 15
+ CPU(15)
+ #endif
+ #if CONF_CPUS > 16
+ #error Unsupported number of CPUs
+ #endif
+ };
+
+ virt-encoder {
+ compatible = "gem5,hdlcd-virt-encoder";
+ port {
+ hdlcd0_virt_input: endpoint@0 {
+ remote-endpoint = <&hdlcd0_output>;
+ };
+ };
+
+ display-timings {
+ native-mode = <&timing0>;
+
+ timing0: timing_1080p60 {
+ /* 1920x1080-60 */
+ clock-frequency = <148500000>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hfront-porch = <148>;
+ hback-porch = <88>;
+ hsync-len = <44>;
+ vfront-porch = <36>;
+ vback-porch = <4>;
+ vsync-len = <5>;
+ };
+ };
+ };
+};
+
+&hdlcd0 {
+ status = "ok";
+
+ port {
+ hdlcd0_output: endpoint@0 {
+ remote-endpoint = <&hdlcd0_virt_input>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00010000;
+
+#include CONF_PLATFORM
+
+#define CPU(n) \
+ cpu@ ## n { \
+ device_type = "cpu"; \
+ compatible = "gem5,armv8", "arm,armv8"; \
+ reg = < n >; \
+ enable-method = "spin-table"; \
+ cpu-release-addr = <0 0x8000fff8>; \
+ };
+
+/ {
+ model = "V2P-AARCH64";
+ compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0x4 0x00000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ #if CONF_CPUS > 0
+ CPU(0)
+ #endif
+ #if CONF_CPUS > 1
+ CPU(1)
+ #endif
+ #if CONF_CPUS > 2
+ CPU(2)
+ #endif
+ #if CONF_CPUS > 3
+ CPU(3)
+ #endif
+ #if CONF_CPUS > 4
+ CPU(4)
+ #endif
+ #if CONF_CPUS > 5
+ CPU(5)
+ #endif
+ #if CONF_CPUS > 6
+ CPU(6)
+ #endif
+ #if CONF_CPUS > 7
+ CPU(7)
+ #endif
+ #if CONF_CPUS > 8
+ CPU(8)
+ #endif
+ #if CONF_CPUS > 9
+ CPU(9)
+ #endif
+ #if CONF_CPUS > 10
+ CPU(10)
+ #endif
+ #if CONF_CPUS > 11
+ CPU(11)
+ #endif
+ #if CONF_CPUS > 12
+ CPU(12)
+ #endif
+ #if CONF_CPUS > 13
+ CPU(13)
+ #endif
+ #if CONF_CPUS > 14
+ CPU(14)
+ #endif
+ #if CONF_CPUS > 15
+ CPU(15)
+ #endif
+ #if CONF_CPUS > 16
+ #error Unsupported number of CPUs
+ #endif
+ };
+};
+
+&hdlcd0 {
+ status = "ok";
+
+ display-timings {
+ native-mode = <&timing0>;
+
+ timing0: timing_1080p60 {
+ /* 1920x1080-60 */
+ clock-frequency = <148500>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hfront-porch = <148>;
+ hback-porch = <88>;
+ hsync-len = <44>;
+ vfront-porch = <36>;
+ vback-porch = <4>;
+ vsync-len = <5>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (c) 2015-2016 ARM Limited
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+/ {
+ arm,hbi = <0x0>;
+ arm,vexpress,site = <0xf>;
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "gem5,gic", "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x2c001000 0 0x1000>,
+ <0 0x2c002000 0 0x1000>,
+ <0 0x2c004000 0 0x2000>,
+ <0 0x2c006000 0 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+
+ timer {
+ compatible = "arm,cortex-a15-timer",
+ "arm,armv7-timer";
+ interrupts = <1 13 0xff01>,
+ <1 14 0xff01>,
+ <1 11 0xff01>;
+ clocks = <&osc_sys>;
+ clock-names="apb_pclk";
+ };
+
+ pci {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+
+ reg = <0x0 0x30000000 0x0 0x10000000>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
+ <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+
+ interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>,
+ <0x000800 0x0 0x0 0 &gic 0 69 1>,
+ <0x001000 0x0 0x0 0 &gic 0 70 1>,
+ <0x001800 0x0 0x0 0 &gic 0 71 1>;
+
+ interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
+ dma-coherent;
+ };
+
+ /* Ths HDLCD controller driver hasn't reached mainline
+ * yet. Disable it by default in the platform until the DT
+ * bindings have stabilize.
+ */
+ hdlcd0: hdlcd@2b000000 {
+ compatible = "arm,hdlcd";
+ reg = <0x0 0x2b000000 0x0 0x1000>;
+ interrupts = <0 63 4>;
+ clocks = <&osc_pxl>;
+ clock-names = "pxlclk";
+
+ status = "disabled";
+ };
+
+ kmi@1c060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x1c060000 0x0 0x1000>;
+ interrupts = <0 12 4>;
+ clocks = <&v2m_clk24mhz>, <&osc_smb>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ kmi@1c070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x1c070000 0x0 0x1000>;
+ interrupts = <0 13 4>;
+ clocks = <&v2m_clk24mhz>, <&osc_smb>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ uart0: uart@1c090000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x1c090000 0x0 0x1000>;
+ interrupts = <0 5 4>;
+ clocks = <&osc_peripheral>, <&osc_smb>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ rtc@1c170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0x1c170000 0x0 0x1000>;
+ interrupts = <0 4 4>;
+ clocks = <&osc_smb>;
+ clock-names = "apb_pclk";
+ };
+
+ v2m_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "v2m:clk24mhz";
+ };
+
+
+ v2m_sysreg: sysreg@1c010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0 0x1c010000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ dcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+ osc_pxl: osc@5 {
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 5>;
+ freq-range = <23750000 1000000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk5";
+ };
+
+ osc_smb: osc@6 {
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 6>;
+ freq-range = <20000000 50000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk6";
+ };
+
+ osc_sys: osc@7 {
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 7>;
+ freq-range = <20000000 60000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk7";
+ };
+ };
+
+
+ mcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+ arm,vexpress,site = <0>;
+
+ osc_peripheral: osc@2 {
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 2>;
+ freq-range = <24000000 24000000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk2";
+ };
+ };
+};
projects / gem5.git / commitdiff