* alpha.md (ev5_e0): Conflict loads and stores.

From-SVN: r25705

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 21a9c221a83799d31557bed88a8ea41311234b4c..f9e698a4cd6b077a59b6f80cfdf6be4e5e0f5a82 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -3,6 +3,8 @@ Thu Mar 11 14:00:58 1999  Richard Henderson  <rth@cygnus.com>
        * alpha.h (HARD_REGNO_MODE_OK): Disallow QI/HImode in fp regs.
        (MODES_TIEABLE_P): Update.
 
+       * alpha.md (ev5_e0): Conflict loads and stores.
+
 Thu Mar 11 13:55:52 1999  Richard Henderson  <rth@cygnus.com>
 
        * machmode.h (smallest_mode_for_size): Prototype.

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 82c108958c2f19c35ccfbbadde6dcd80f7579b38..55bdc11c5513d554cf50a46efb55faf0e645d436 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -155,13 +155,18 @@
 
 ; Memory takes at least 2 clocks.  Return one from here and fix up with
 ; user-defined latencies in adjust_cost.
-; ??? How to: "An instruction of class LD cannot be issued in the _second_
-; cycle after an instruction of class ST is issued."
 (define_function_unit "ev5_ebox" 2 0
   (and (eq_attr "cpu" "ev5")
        (eq_attr "type" "ild,fld,ldsym"))
   1 1)
 
+; Loads can dual issue with one another, but loads and stores do not mix.
+(define_function_unit "ev5_e0" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "ild,fld,ldsym"))
+  1 1
+  [(eq_attr "type" "ist,fst")])
+
 ; Stores, shifts, multiplies can only issue to E0
 (define_function_unit "ev5_e0" 1 0
   (and (eq_attr "cpu" "ev5")