sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move...

diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c241b631db6b6df62328ca757e5b0464980807a7 100644 (file)
--- a/misoclib/mem/sdram/core/__init__.py
+++ b/misoclib/mem/sdram/core/__init__.py
@@ -0,0 +1,30 @@
+from migen.fhdl.std import *
+from migen.genlib.record import *
+from migen.bank.description import *
+
+from misoclib.mem.sdram.phy import dfii
+from misoclib.mem.sdram.core import minicon, lasmicon
+from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar
+
+class SDRAMCore(Module, AutoCSR):
+       def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing):
+               # DFI
+               self.submodules.dfii = dfii.DFIInjector(phy, sdram_geom.mux_a, sdram_geom.bank_a)
+               self.comb += Record.connect(self.dfii.master, phy.dfi)
+
+               # LASMICON
+               if ramcon_type == "lasmicon":
+                       self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing)
+                       self.comb += Record.connect(controller.dfi, self.dfii.slave)
+
+                       self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits)
+
+               # MINICON
+               elif ramcon_type == "minicon":
+                       if self.with_l2:
+                               raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))")
+
+                       self.submodules.controller = controller = minicon.Minicon(phy, sdram_geom, sdram_timing)
+                       self.comb += Record.connect(controller.dfi, self.dfii.slave)
+               else:
+                       raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))

diff --git a/misoclib/mem/sdram/phy/initsequence.py b/misoclib/mem/sdram/phy/initsequence.py
index 3dc561d97bd53f7bfc8567acf2aea667ef2d2eac..a2eb466644961426e5ffb092eb6a7e1023d74c3c 100644 (file)
--- a/misoclib/mem/sdram/phy/initsequence.py
+++ b/misoclib/mem/sdram/phy/initsequence.py
@@ -14,18 +14,18 @@ def get_sdram_phy_header(sdram_phy):
                r += """
 static void command_p{n}(int cmd)
 {{
-       dfii_pi{n}_command_write(cmd);
-       dfii_pi{n}_command_issue_write(1);
+       sdram_dfii_pi{n}_command_write(cmd);
+       sdram_dfii_pi{n}_command_issue_write(1);
 }}""".format(n=str(n))
        r += "\n\n"
 
        # rd/wr access macros
        r += """
-#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
-#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
+#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
+#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
 
-#define dfii_pird_baddress_write(X) dfii_pi{rdphase}_baddress_write(X)
-#define dfii_piwr_baddress_write(X) dfii_pi{wrphase}_baddress_write(X)
+#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
+#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
 
 #define command_prd(X) command_p{rdphase}(X)
 #define command_pwr(X) command_p{wrphase}(X)
@@ -35,24 +35,24 @@ static void command_p{n}(int cmd)
        #
        # sdrrd/sdrwr functions utilities
        #
-       r += "#define DFII_PIX_DATA_SIZE CSR_DFII_PI0_WRDATA_SIZE\n"
-       dfii_pix_wrdata_addr = []
+       r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
+       sdram_dfii_pix_wrdata_addr = []
        for n in range(nphases):
-               dfii_pix_wrdata_addr.append("CSR_DFII_PI{n}_WRDATA_ADDR".format(n=n))
+               sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
        r += """
-const unsigned int dfii_pix_wrdata_addr[{n}] = {{
-       {dfii_pix_wrdata_addr}
+const unsigned int sdram_dfii_pix_wrdata_addr[{n}] = {{
+       {sdram_dfii_pix_wrdata_addr}
 }};
-""".format(n=nphases, dfii_pix_wrdata_addr=",\n\t".join(dfii_pix_wrdata_addr))
+""".format(n=nphases, sdram_dfii_pix_wrdata_addr=",\n\t".join(sdram_dfii_pix_wrdata_addr))
 
-       dfii_pix_rddata_addr = []
+       sdram_dfii_pix_rddata_addr = []
        for n in range(nphases):
-               dfii_pix_rddata_addr.append("CSR_DFII_PI{n}_RDDATA_ADDR".format(n=n))
+               sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
        r += """
-const unsigned int dfii_pix_rddata_addr[{n}] = {{
-       {dfii_pix_rddata_addr}
+const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
+       {sdram_dfii_pix_rddata_addr}
 }};
-""".format(n=nphases, dfii_pix_rddata_addr=",\n\t".join(dfii_pix_rddata_addr))
+""".format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
        r +="\n"
 
        # init sequence
@@ -209,10 +209,10 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
        r += "static void init_sequence(void)\n{\n"
        for comment, a, ba, cmd, delay in init_sequence:
                r += "\t/* {0} */\n".format(comment)
-               r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
-               r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
+               r += "\tsdram_dfii_pi0_address_write({0:#x});\n".format(a)
+               r += "\tsdram_dfii_pi0_baddress_write({0:d});\n".format(ba)
                if cmd[:12] == "DFII_CONTROL":
-                       r += "\tdfii_control_write({0});\n".format(cmd)
+                       r += "\tsdram_dfii_control_write({0});\n".format(cmd)
                else:
                        r += "\tcommand_p0({0});\n".format(cmd)
                if delay:

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 5d033fb7efd277506bf9406e2a97ce90ac4856c0..4fbfb73daa3cc03aac74ddc9c5f108fec2305463 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -3,16 +3,13 @@ from migen.bus import wishbone, csr
 from migen.genlib.record import *
 
 from misoclib.mem.sdram.bus import dfi, lasmibus
-from misoclib.mem.sdram.phy import dfii
-from misoclib.mem.sdram.core import minicon, lasmicon
-from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar
+from misoclib.mem.sdram.core import SDRAMCore
 from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
 from misoclib.soc import SoC, mem_decoder
 
 class SDRAMSoC(SoC):
        csr_map = {
-               "dfii":                                 7,
-               "controller":                   8,
+               "sdram":                                8,
                "wishbone2lasmi":               9,
                "memtest_w":                    10,
                "memtest_r":                    11
@@ -39,48 +36,34 @@ class SDRAMSoC(SoC):
                        raise FinalizeError
                self._sdram_phy_registered = True
 
-               # DFI
-               self.submodules.dfii = dfii.DFIInjector(phy, sdram_geom.mux_a, sdram_geom.bank_a)
-               self.comb += Record.connect(self.dfii.master, phy.dfi)
+               # Core
+               self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, sdram_geom, sdram_timing)
 
-               # LASMICON
+               # LASMICON frontend
                if self.ramcon_type == "lasmicon":
-                       self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing)
-                       self.comb += Record.connect(controller.dfi, self.dfii.slave)
-
-                       self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits)
-
                        if self.with_memtest:
-                               self.submodules.memtest_w = memtest.MemtestWriter(crossbar.get_master())
-                               self.submodules.memtest_r = memtest.MemtestReader(crossbar.get_master())
+                               self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
+                               self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
 
                        if self.with_l2:
-                               self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, crossbar.get_master())
-                               lasmic = self.controller.lasmic
+                               self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
+                               lasmic = self.sdram.controller.lasmic
                                sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
                                self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)
 
-               # MINICON
+               # MINICON frontend
                elif self.ramcon_type == "minicon":
-                       if self.with_l2:
-                               raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))")
-
-                       self.submodules.controller = controller = minicon.Minicon(phy, sdram_geom, sdram_timing)
-                       self.comb += Record.connect(controller.dfi, self.dfii.slave)
-
-                       sdram_width = flen(controller.bus.dat_r)
+                       sdram_width = flen(self.sdram.controller.bus.dat_r)
                        sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
 
                        if sdram_width == 32:
-                               self.register_mem("sdram", self.mem_map["sdram"], controller.bus, sdram_size)
+                               self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, sdram_size)
                        elif sdram_width < 32:
                                self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
-                               self.comb += Record.connect(downconverter.wishbone_o, controller.bus)
+                               self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
                                self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, sdram_size)
                        else:
                                raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
-               else:
-                       raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
 
        def do_finalize(self):
                if not self._sdram_phy_registered:

diff --git a/software/bios/main.c b/software/bios/main.c
index 32f77a43f2eacfc547bd0b1b41e092763b85374e..fad8e4efc324924026c3e69fda449395c5a69b65 100644 (file)
--- a/software/bios/main.c
+++ b/software/bios/main.c
@@ -374,7 +374,7 @@ static void do_command(char *c)
        else if(strcmp(token, "wcsr") == 0) wcsr(get_token(&c), get_token(&c));
 #endif
 
-#ifdef DFII_BASE
+#ifdef SDRAM_BASE
        else if(strcmp(token, "sdrrow") == 0) sdrrow(get_token(&c));
        else if(strcmp(token, "sdrsw") == 0) sdrsw();
        else if(strcmp(token, "sdrhw") == 0) sdrhw();
@@ -525,7 +525,7 @@ int main(int i, char **c)
 #ifdef ETHMAC_BASE
        ethreset();
 #endif
-#ifdef DFII_BASE
+#ifdef SDRAM_BASE
        sdr_ok = sdrinit();
 #else
        sdr_ok = 1;

diff --git a/software/bios/sdram.c b/software/bios/sdram.c
index 140e11ef2bd4f001d6975a41bcf0f85f8e0b715a..8e2917630e7d9ee821f08ea5d640b73dbdda7247 100644 (file)
--- a/software/bios/sdram.c
+++ b/software/bios/sdram.c
@@ -1,5 +1,5 @@
 #include <generated/csr.h>
-#ifdef DFII_BASE
+#ifdef SDRAM_BASE
 
 #include <stdio.h>
 #include <stdlib.h>
@@ -26,13 +26,13 @@ static void cdelay(int i)
 
 void sdrsw(void)
 {
-       dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
+       sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
        printf("SDRAM now under software control\n");
 }
 
 void sdrhw(void)
 {
-       dfii_control_write(DFII_CONTROL_SEL);
+       sdram_dfii_control_write(DFII_CONTROL_SEL);
        printf("SDRAM now under hardware control\n");
 }
 
@@ -42,8 +42,8 @@ void sdrrow(char *_row)
        unsigned int row;
 
        if(*_row == 0) {
-               dfii_pi0_address_write(0x0000);
-               dfii_pi0_baddress_write(0);
+               sdram_dfii_pi0_address_write(0x0000);
+               sdram_dfii_pi0_baddress_write(0);
                command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
                cdelay(15);
                printf("Precharged\n");
@@ -53,8 +53,8 @@ void sdrrow(char *_row)
                        printf("incorrect row\n");
                        return;
                }
-               dfii_pi0_address_write(row);
-               dfii_pi0_baddress_write(0);
+               sdram_dfii_pi0_address_write(row);
+               sdram_dfii_pi0_baddress_write(0);
                command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
                cdelay(15);
                printf("Activated row %d\n", row);
@@ -76,7 +76,7 @@ void sdrrdbuf(int dq)
 
        for(p=0;p<DFII_NPHASES;p++)
                for(i=first_byte;i<DFII_PIX_DATA_SIZE;i+=step)
-                       printf("%02x", MMPTR(dfii_pix_rddata_addr[p]+4*i));
+                       printf("%02x", MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i));
        printf("\n");
 }
 
@@ -105,8 +105,8 @@ void sdrrd(char *startaddr, char *dq)
                }
        }
 
-       dfii_pird_address_write(addr);
-       dfii_pird_baddress_write(0);
+       sdram_dfii_pird_address_write(addr);
+       sdram_dfii_pird_baddress_write(0);
        command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
        cdelay(15);
        sdrrdbuf(_dq);
@@ -134,13 +134,13 @@ void sdrrderr(char *count)
        for(i=0;i<DFII_NPHASES*DFII_PIX_DATA_SIZE;i++)
                        errs[i] = 0;
        for(addr=0;addr<16;addr++) {
-               dfii_pird_address_write(addr*8);
-               dfii_pird_baddress_write(0);
+               sdram_dfii_pird_address_write(addr*8);
+               sdram_dfii_pird_baddress_write(0);
                command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
                cdelay(15);
                for(p=0;p<DFII_NPHASES;p++)
                        for(i=0;i<DFII_PIX_DATA_SIZE;i++)
-                               prev_data[p*DFII_PIX_DATA_SIZE+i] = MMPTR(dfii_pix_rddata_addr[p]+4*i);
+                               prev_data[p*DFII_PIX_DATA_SIZE+i] = MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i);
 
                for(j=0;j<_count;j++) {
                        command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
@@ -149,7 +149,7 @@ void sdrrderr(char *count)
                                for(i=0;i<DFII_PIX_DATA_SIZE;i++) {
                                        unsigned char new_data;
 
-                                       new_data = MMPTR(dfii_pix_rddata_addr[p]+4*i);
+                                       new_data = MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i);
                                        errs[p*DFII_PIX_DATA_SIZE+i] |= prev_data[p*DFII_PIX_DATA_SIZE+i] ^ new_data;
                                        prev_data[p*DFII_PIX_DATA_SIZE+i] = new_data;
                                }
@@ -184,10 +184,10 @@ void sdrwr(char *startaddr)
 
        for(p=0;p<DFII_NPHASES;p++)
                for(i=0;i<DFII_PIX_DATA_SIZE;i++)
-                       MMPTR(dfii_pix_wrdata_addr[p]+4*i) = 0x10*p + i;
+                       MMPTR(sdram_dfii_pix_wrdata_addr[p]+4*i) = 0x10*p + i;
 
-       dfii_piwr_address_write(addr);
-       dfii_piwr_baddress_write(0);
+       sdram_dfii_piwr_address_write(addr);
+       sdram_dfii_piwr_baddress_write(0);
        command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
 }
 
@@ -195,16 +195,16 @@ void sdrwr(char *startaddr)
 
 void sdrwlon(void)
 {
-       dfii_pi0_address_write(DDR3_MR1 | (1 << 7));
-       dfii_pi0_baddress_write(1);
+       sdram_dfii_pi0_address_write(DDR3_MR1 | (1 << 7));
+       sdram_dfii_pi0_baddress_write(1);
        command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
        ddrphy_wlevel_en_write(1);
 }
 
 void sdrwloff(void)
 {
-       dfii_pi0_address_write(DDR3_MR1);
-       dfii_pi0_baddress_write(1);
+       sdram_dfii_pi0_address_write(DDR3_MR1);
+       sdram_dfii_pi0_baddress_write(1);
        command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
        ddrphy_wlevel_en_write(0);
 }
@@ -223,7 +223,7 @@ static int write_level(int *delay, int *high_skew)
        sdrwlon();
        cdelay(100);
        for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) {
-               dq_address = dfii_pix_rddata_addr[0]+4*(DFII_PIX_DATA_SIZE/2-1-i);
+               dq_address = sdram_dfii_pix_rddata_addr[0]+4*(DFII_PIX_DATA_SIZE/2-1-i);
                ddrphy_dly_sel_write(1 << i);
                ddrphy_wdly_dq_rst_write(1);
                ddrphy_wdly_dqs_rst_write(1);
@@ -325,22 +325,22 @@ static void read_delays(void)
        }
 
        /* Activate */
-       dfii_pi0_address_write(0);
-       dfii_pi0_baddress_write(0);
+       sdram_dfii_pi0_address_write(0);
+       sdram_dfii_pi0_baddress_write(0);
        command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
        cdelay(15);
 
        /* Write test pattern */
        for(p=0;p<DFII_NPHASES;p++)
                for(i=0;i<DFII_PIX_DATA_SIZE;i++)
-                       MMPTR(dfii_pix_wrdata_addr[p]+4*i) = prs[DFII_PIX_DATA_SIZE*p+i];
-       dfii_piwr_address_write(0);
-       dfii_piwr_baddress_write(0);
+                       MMPTR(sdram_dfii_pix_wrdata_addr[p]+4*i) = prs[DFII_PIX_DATA_SIZE*p+i];
+       sdram_dfii_piwr_address_write(0);
+       sdram_dfii_piwr_baddress_write(0);
        command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
 
        /* Calibrate each DQ in turn */
-       dfii_pird_address_write(0);
-       dfii_pird_baddress_write(0);
+       sdram_dfii_pird_address_write(0);
+       sdram_dfii_pird_baddress_write(0);
        for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) {
                ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE/2-i-1));
                delay = 0;
@@ -352,9 +352,9 @@ static void read_delays(void)
                        cdelay(15);
                        working = 1;
                        for(p=0;p<DFII_NPHASES;p++) {
-                               if(MMPTR(dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
+                               if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
                                        working = 0;
-                               if(MMPTR(dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
+                               if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
                                        working = 0;
                        }
                        if(working)
@@ -376,9 +376,9 @@ static void read_delays(void)
                        cdelay(15);
                        working = 1;
                        for(p=0;p<DFII_NPHASES;p++) {
-                               if(MMPTR(dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
+                               if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
                                        working = 0;
-                               if(MMPTR(dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
+                               if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
                                        working = 0;
                        }
                        if(!working)
@@ -399,8 +399,8 @@ static void read_delays(void)
        }
 
        /* Precharge */
-       dfii_pi0_address_write(0);
-       dfii_pi0_baddress_write(0);
+       sdram_dfii_pi0_address_write(0);
+       sdram_dfii_pi0_baddress_write(0);
        command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
        cdelay(15);
 
@@ -479,7 +479,7 @@ int sdrinit(void)
        if(!sdrlevel())
                return 0;
 #endif
-       dfii_control_write(DFII_CONTROL_SEL);
+       sdram_dfii_control_write(DFII_CONTROL_SEL);
        if(!memtest())
                return 0;