}
}
-static uint32_t*
-texture_ptr(struct tu_descriptor_state *descriptors_state,
- const struct tu_descriptor_map *map, unsigned i)
+static void
+write_tex_const(struct tu_cmd_buffer *cmd,
+ uint32_t *dst,
+ struct tu_descriptor_state *descriptors_state,
+ const struct tu_descriptor_map *map,
+ unsigned i)
{
assert(descriptors_state->valid & (1 << map->set[i]));
switch (layout->type) {
case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
- return &set->mapped_ptr[layout->offset / 4];
case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
- return &set->mapped_ptr[layout->offset / 4];
+ case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
+ memcpy(dst, &set->mapped_ptr[layout->offset / 4], A6XX_TEX_CONST_DWORDS*4);
+ break;
default:
unreachable("unimplemented descriptor type");
break;
}
+
+ if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
+ const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
+ uint32_t a = cmd->state.subpass->input_attachments[map->value[i]].attachment;
+
+ assert(cmd->state.pass->attachments[a].needs_gmem);
+ dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
+ dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
+ dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
+ dst[2] |=
+ A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
+ A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * tiling->buffer_cpp[a]);
+ dst[3] = 0;
+ dst[4] = 0x100000 + tiling->gmem_offsets[a];
+ dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
+ for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
+ dst[i] = 0;
+ }
}
static uint64_t
return result;
for (unsigned i = 0; i < link->texture_map.num; i++) {
- memcpy(&tex_const.map[A6XX_TEX_CONST_DWORDS*i],
- texture_ptr(descriptors_state, &link->texture_map, i),
- A6XX_TEX_CONST_DWORDS*4);
+ write_tex_const(cmd,
+ &tex_const.map[A6XX_TEX_CONST_DWORDS*i],
+ descriptors_state, &link->texture_map, i);
}
/* allocate and fill sampler state */
}
static unsigned
-map_add(struct tu_descriptor_map *map, int set, int binding)
+map_add(struct tu_descriptor_map *map, int set, int binding, int value)
{
unsigned index;
for (index = 0; index < map->num; index++) {
map->set[index] = set;
map->binding[index] = binding;
+ map->value[index] = value;
map->num = MAX2(map->num, index + 1);
return index;
}
if (is_sampler) {
instr->sampler_index = map_add(&shader->sampler_map,
deref->var->data.descriptor_set,
- deref->var->data.binding);
+ deref->var->data.binding,
+ 0);
instr->sampler_index += base_index;
} else {
instr->texture_index = map_add(&shader->texture_map,
deref->var->data.descriptor_set,
- deref->var->data.binding);
+ deref->var->data.binding,
+ deref->var->data.index);
instr->texture_index += base_index;
instr->texture_array_size = array_elements;
}
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
/* skip index 0 which is used for push constants */
- index = map_add(&shader->ubo_map, set, binding) + 1;
+ index = map_add(&shader->ubo_map, set, binding, 0) + 1;
break;
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
- index = map_add(&shader->ssbo_map, set, binding);
+ index = map_add(&shader->ssbo_map, set, binding, 0);
break;
default:
tu_finishme("unsupported desc_type for vulkan_resource_index");
NIR_PASS_V(nir, nir_lower_system_values);
NIR_PASS_V(nir, nir_lower_frexp);
+ if (stage == MESA_SHADER_FRAGMENT)
+ NIR_PASS_V(nir, nir_lower_input_attachments, true);
+
NIR_PASS_V(nir, tu_lower_io, shader);
NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);