sim: v850: fix SMP compile

The igen tool sets up the SD & CPU defines for code fragments to use,
but v850 was expecting "sd".  Change all the igen related code to use
SD so it actually compiles, and fix a few places to use "CPU" instead
of hardcoding cpu0.

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 5783f8606b30bb349ca7fd4f75734a034fa8ca7b..69db8aaaa53d8bb99577cfad1302f567c07c3351 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -48,6 +48,9 @@ int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
 #define SIZE_VALUES 11
 #endif
 
+/* TODO: This file largely assumes a single CPU.  */
+#define CPU STATE_CPU (sd, 0)
+
 
 uint32_t   trace_values[3];
 int          trace_num_values;

diff --git a/sim/v850/v850-sim.h b/sim/v850/v850-sim.h
index 35032306235fd04603ea058d79e07430721f840f..6bd5fcfcc5c6ab5b65000d7ed31b53bb416dc366 100644 (file)
--- a/sim/v850/v850-sim.h
+++ b/sim/v850/v850-sim.h
@@ -91,9 +91,9 @@ nia = PC
 #define GR  (V850_SIM_CPU (CPU)->reg.regs)
 #define SR  (V850_SIM_CPU (CPU)->reg.sregs)
 #define VR  (V850_SIM_CPU (CPU)->reg.vregs)
-#define MPU0_SR  (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu0_sregs)
-#define MPU1_SR  (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu1_sregs)
-#define FPU_SR   (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.fpu_sregs)
+#define MPU0_SR  (V850_SIM_CPU (CPU)->reg.mpu0_sregs)
+#define MPU1_SR  (V850_SIM_CPU (CPU)->reg.mpu1_sregs)
+#define FPU_SR   (V850_SIM_CPU (CPU)->reg.fpu_sregs)
 
 /* old */
 #define State    (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg)
@@ -379,7 +379,7 @@ enum FPU_COMPARE {
 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 
 #define IMEM16_IMMED(EA,N) \
-sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
+sim_core_read_aligned_2 (STATE_CPU (SD, 0), \
                         PC, exec_map, (EA) + (N) * 2)
 
 #define load_mem(ADDR,LEN) \

diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 6bfabc08ea0a98da36e63ecd58cc5c9c6a0e71f7..bd8de8e2790d9bc335973d31ef1b0a6ebc5315a5 100644 (file)
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -304,10 +304,10 @@ rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
 
   addr = GR[reg1];
 
-  if (mpu_load_mem_test(sd, addr, 4, reg1) 
-      && mpu_store_mem_test(sd, addr, 4, reg1))
+  if (mpu_load_mem_test (SD, addr, 4, reg1)
+      && mpu_store_mem_test (SD, addr, 4, reg1))
     {
-      token = load_data_mem (sd, addr, 4);
+      token = load_data_mem (SD, addr, 4);
 
       TRACE_ALU_INPUT2 (token, GR[reg2]);
 
@@ -321,12 +321,12 @@ rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
 
       if (result == 0)
        {
-         store_data_mem (sd, addr, 4, GR[reg3]);
+         store_data_mem (SD, addr, 4, GR[reg3]);
          GR[reg3] = token;
        }
       else
        {
-         store_data_mem (sd, addr, 4, token);
+         store_data_mem (SD, addr, 4, token);
          GR[reg3] = token;
        }
   
@@ -584,7 +584,7 @@ rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq
 
   divide_by   = GR[reg1];
   divide_this = GR[reg2];
-  v850_div (sd, divide_by, divide_this, &quotient, &remainder);
+  v850_div (SD, divide_by, divide_this, &quotient, &remainder);
   GR[reg2] = quotient;
   GR[reg3] = remainder;
 
@@ -608,7 +608,7 @@ rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
   
   divide_by   = GR[reg1];
   divide_this = GR[reg2];
-  v850_divu (sd, divide_by, divide_this, &quotient, &remainder);
+  v850_divu (SD, divide_by, divide_this, &quotient, &remainder);
   GR[reg2] = quotient;
   GR[reg3] = remainder;
 
@@ -845,7 +845,7 @@ rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 *v850e3v5
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = EXTEND8 (load_data_mem (sd, addr, 1));
+  uint32_t result = EXTEND8 (load_data_mem (SD, addr, 1));
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -862,7 +862,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 "ld.h <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = EXTEND16 (load_data_mem (sd, addr, 2));
+  uint32_t result = EXTEND16 (load_data_mem (SD, addr, 2));
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -879,7 +879,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 "ld.w <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 4);
+  uint32_t result = load_data_mem (SD, addr, 4);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -889,10 +889,10 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 "ld.dw <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 4);
+  uint32_t result = load_data_mem (SD, addr, 4);
   GR[reg3] = result;
   TRACE_LD (addr, result);
-  result = load_data_mem (sd, addr + 4, 4);
+  result = load_data_mem (SD, addr + 4, 4);
   GR[reg3 + 1] = result;
   TRACE_LD (addr + 4, result);
 }
@@ -914,7 +914,7 @@ rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 "ld.bu <disp23>[r<reg1>], r<reg3>"
 { 
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 1);
+  uint32_t result = load_data_mem (SD, addr, 1);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -936,7 +936,7 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 "ld.hu <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 2);
+  uint32_t result = load_data_mem (SD, addr, 2);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -1529,7 +1529,7 @@ rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar
 "sar r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_sar(sd, GR[reg1], GR[reg2], &GR[reg3]); 
+  v850_sar (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1568,7 +1568,7 @@ rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd
 "satadd r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_satadd (sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_satadd (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1588,7 +1588,7 @@ rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub
 "satsub r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_satsub (sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_satsub (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1829,7 +1829,7 @@ rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl
 "shl r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_shl(sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_shl (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1841,7 +1841,7 @@ rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr
 "shr r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_shr(sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_shr (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -2036,7 +2036,7 @@ rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 "st.b r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 1, GR[reg3]);
+  store_data_mem (SD, addr, 1, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
 
@@ -2052,7 +2052,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 "st.h r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 2, GR[reg3]);
+  store_data_mem (SD, addr, 2, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
 
@@ -2068,7 +2068,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 "st.w r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 4, GR[reg3]);
+  store_data_mem (SD, addr, 4, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
 
@@ -2077,9 +2077,9 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 "st.dw r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 4, GR[reg3]);
+  store_data_mem (SD, addr, 4, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
-  store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]);
+  store_data_mem (SD, addr + 4, 4, GR[reg3 + 1]);
   TRACE_ST (addr + 4, GR[reg3 + 1]);
 }
 
@@ -2376,7 +2376,7 @@ rrrr,011111100000 + wwww,010001011000:F_I:::absf_d
   TRACE_FP_INPUT_FPU1 (&wop);
 
   status = sim_fpu_abs (&ans, &wop);
-  check_invalid_snan(sd, status, 1);
+  check_invalid_snan (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
 
@@ -2396,7 +2396,7 @@ rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s
   TRACE_FP_INPUT_FPU1 (&wop);
 
   status = sim_fpu_abs (&ans, &wop);
-  check_invalid_snan(sd, status, 0);
+  check_invalid_snan (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2418,7 +2418,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d
   status = sim_fpu_add (&ans, &wop1, &wop2);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2440,7 +2440,7 @@ rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s
   status = sim_fpu_add (&ans, &wop1, &wop2);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2520,7 +2520,7 @@ rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
   sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
   TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
 
-  result = v850_float_compare(sd, FFFF, wop2, wop1, 1);
+  result = v850_float_compare (SD, FFFF, wop2, wop1, 1);
 
   if (result)  
     SET_FPCC(bbb);
@@ -2545,7 +2545,7 @@ rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
   sim_fpu_32to( &wop2, GR[reg2] );
   TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
 
-  result = v850_float_compare(sd, FFFF, wop2, wop1, 0);
+  result = v850_float_compare (SD, FFFF, wop2, wop1, 0);
 
   if (result)  
     SET_FPCC(bbb);
@@ -2571,7 +2571,7 @@ rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans>>32L;
@@ -2592,7 +2592,7 @@ rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds
 
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2614,7 +2614,7 @@ rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND());
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -2636,7 +2636,7 @@ rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
   sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 1);
+  check_cvt_if (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2658,7 +2658,7 @@ rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
   sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 0);
+  check_cvt_if (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2677,7 +2677,7 @@ rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd
   TRACE_FP_INPUT_FPU1 (&wop);
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  check_cvt_ff(sd, status, 1);
+  check_cvt_ff (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2699,7 +2699,7 @@ rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans >> 32L;
@@ -2722,7 +2722,7 @@ rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -2741,7 +2741,7 @@ rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd
   sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 1);
+  check_cvt_if (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2760,7 +2760,7 @@ rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws
   sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 0);
+  check_cvt_if (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2782,7 +2782,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d
   status = sim_fpu_div (&ans, &wop2, &wop1);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2804,7 +2804,7 @@ rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s
   status = sim_fpu_div (&ans, &wop2, &wop1);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2828,7 +2828,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s
   status |= sim_fpu_add (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2852,7 +2852,7 @@ rrrrr,111111,RRRRR + wwwww,10011100000:F_I:::fmaf_s
   status |= sim_fpu_add (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2874,7 +2874,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
     {
       if (FPSR & FPSR_XEV)
        {
-         SignalExceptionFPE(sd, 1);
+         SignalExceptionFPE (SD, 1);
        }
       else
        {
@@ -2912,7 +2912,7 @@ rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s
     {
       if (FPSR & FPSR_XEV)
        {
-         SignalExceptionFPE(sd, 0);
+         SignalExceptionFPE (SD, 0);
        }
       else
        {
@@ -2950,7 +2950,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d
     {
       if (FPSR & FPSR_XEV)
        {
-         SignalExceptionFPE(sd, 1);
+         SignalExceptionFPE (SD, 1);
        }
       else
        {
@@ -2988,7 +2988,7 @@ rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s
     {
       if (FPSR & FPSR_XEV)
        {
-         SignalExceptionFPE(sd, 0);
+         SignalExceptionFPE (SD, 0);
        }
       else
        {
@@ -3029,7 +3029,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s
   status |= sim_fpu_sub (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3054,7 +3054,7 @@ rrrrr,111111,RRRRR + wwwww,10011100010:F_I:::fmsf_s
   status |= sim_fpu_sub (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3076,7 +3076,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
   status = sim_fpu_mul (&ans, &wop1, &wop2);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3098,7 +3098,7 @@ rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s
   status = sim_fpu_mul (&ans, &wop1, &wop2);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3118,7 +3118,7 @@ rrrr,011111100001 + wwww,010001011000:F_I:::negf_d
 
   status = sim_fpu_neg (&ans, &wop);
 
-  check_invalid_snan(sd, status, 1);
+  check_invalid_snan (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3138,7 +3138,7 @@ rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s
 
   status = sim_fpu_neg (&ans, &wop);
 
-  check_invalid_snan(sd, status, 0);
+  check_invalid_snan (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3164,7 +3164,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3190,7 +3190,7 @@ rrrrr,111111,RRRRR + wwwww,10011100100:F_I:::fnmaf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3217,7 +3217,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3244,7 +3244,7 @@ rrrrr,111111,RRRRR + wwwww,10011100110:F_I:::fnmsf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3265,7 +3265,7 @@ rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3286,7 +3286,7 @@ rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3310,7 +3310,7 @@ rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3334,7 +3334,7 @@ rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3355,7 +3355,7 @@ rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d
   status = sim_fpu_sqrt (&ans, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3376,7 +3376,7 @@ rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s
   status = sim_fpu_sqrt (&ans, &wop);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3398,7 +3398,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d
   status = sim_fpu_sub (&ans, &wop2, &wop1);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3420,7 +3420,7 @@ rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
   status = sim_fpu_sub (&ans, &wop2, &wop1);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3458,7 +3458,7 @@ rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
 
   status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans>>32L;
@@ -3480,7 +3480,7 @@ rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
 
   status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans>>32L;
@@ -3502,7 +3502,7 @@ rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
 
   status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3523,7 +3523,7 @@ rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
 
   status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3584,7 +3584,7 @@ rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
 
   status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3605,7 +3605,7 @@ rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
 
   status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3617,7 +3617,7 @@ rrrrr,111111,iiiii+wwwww,00011000100:VII:::rotl_imm
 "rotl imm5, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT1 (GR[reg2]);
-  v850_rotl (sd, imm5, GR[reg2], & GR[reg3]);
+  v850_rotl (SD, imm5, GR[reg2], & GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -3626,7 +3626,7 @@ rrrrr,111111,RRRRR+wwwww,00011000110:VII:::rotl
 "rotl r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_rotl (sd, GR[reg1], GR[reg2], & GR[reg3]);
+  v850_rotl (SD, GR[reg1], GR[reg2], & GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -3636,7 +3636,7 @@ rrrrr,111111,RRRRR+bbbb,B,0001001,BBB,0:IX:::bins_top
 "bins r<reg1>, <bit13> + 16, <bit4> - <bit13> + 17, r<reg2>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
-  v850_bins (sd, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]);
+  v850_bins (SD, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]);
   TRACE_ALU_RESULT1 (GR[reg2]);
 }
 
@@ -3645,7 +3645,7 @@ rrrrr,111111,RRRRR+bbbb,B,0001011,BBB,0:IX:::bins_middle
 "bins r<reg1>, <bit13>, <bit4> - <bit13> + 17, r<reg2>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
-  v850_bins (sd, GR[reg1], bit13, bit4 + 16, & GR[reg2]);
+  v850_bins (SD, GR[reg1], bit13, bit4 + 16, & GR[reg2]);
   TRACE_ALU_RESULT1 (GR[reg2]);
 }
 
@@ -3654,7 +3654,7 @@ rrrrr,111111,RRRRR+bbbb,B,0001101,BBB,0:IX:::bins_bottom
 "bins r<reg1>, <bit13>, <bit4> - <bit13> + 1, r<reg2>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
-  v850_bins (sd, GR[reg1], bit13, bit4, & GR[reg2]);
+  v850_bins (SD, GR[reg1], bit13, bit4, & GR[reg2]);
   TRACE_ALU_RESULT1 (GR[reg2]);
 }