radeonsi/gfx9: merged shaders have scratch offset at the beginning

also, screen wasn't initialized for compute shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 33ebe2e7d97ecee702f69b3d7d43c8d9b71371b0..2b2efaeadcbe82ac7ee5a7c9403379dce63357bc 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -113,6 +113,7 @@ static void si_create_compute_state_async(void *job, int thread_index)
 
        memset(&sel, 0, sizeof(sel));
 
+       sel.screen = program->screen;
        tgsi_scan_shader(program->tokens, &sel.info);
        sel.tokens = program->tokens;
        sel.type = PIPE_SHADER_COMPUTE;

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 593383e3da1065dbe1eb76d6bc2d806de3417423..574244b484c0b18cfd5cfdb756c85bccd45d51fd 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -100,6 +100,17 @@ enum {
        LOCAL_ADDR_SPACE = 3,
 };
 
+static bool is_merged_shader(struct si_shader *shader)
+{
+       if (shader->selector->screen->b.chip_class <= VI)
+               return false;
+
+       return shader->key.as_ls ||
+              shader->key.as_es ||
+              shader->selector->type == PIPE_SHADER_TESS_CTRL ||
+              shader->selector->type == PIPE_SHADER_GEOMETRY;
+}
+
 /**
  * Returns a unique index for a semantic name and index. The index must be
  * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
@@ -7689,7 +7700,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
        }
 
        /* Add the scratch offset to input SGPRs. */
-       if (shader->config.scratch_bytes_per_wave)
+       if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
                shader->info.num_input_sgprs += 1; /* scratch byte offset */
 
        /* Calculate the number of fragment input VGPRs. */