radv: force cs/ps/l2 flush at end of command stream. (v2)

This seems like a workaround, but we don't see the bug on CIK/VI.

On SI with the dEQP-VK.memory.pipeline_barrier.host_read_transfer_dst.*
tests, when one tests complete, the first flush at the start of the next
test causes a VM fault as we've destroyed the VM, but we end up flushing
the compute shader then, and it must still be in the process of doing
something.

Could also be a kernel difference between SI and CIK.

v2: hit this with a bigger hammer. This fixes a bunch of hangs
in the vk cts with the robustness tests.

Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e7bff2a88cf551fe3300937178030a86cf0f6bd1..ad73413323f6148933717a7b89ea9b42a9118bb9 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2232,8 +2232,11 @@ VkResult radv_EndCommandBuffer(
 {
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
-       if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
+       if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
+               if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
+                       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
                si_emit_cache_flush(cmd_buffer);
+       }
 
        if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
            cmd_buffer->record_fail)