glsl: Add a lowering pass for 64-bit integer division
authorIan Romanick <ian.d.romanick@intel.com>
Tue, 18 Oct 2016 00:55:18 +0000 (17:55 -0700)
committerIan Romanick <ian.d.romanick@intel.com>
Fri, 20 Jan 2017 23:41:23 +0000 (15:41 -0800)
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/compiler/glsl/ir_optimization.h
src/compiler/glsl/lower_int64.cpp

index e4f78f038fddab176ecbf904c0290c7ca88af886..3f0ef7d280c6ab508d6873a24c9e034a2a3deb6c 100644 (file)
@@ -53,6 +53,7 @@
 /* Opertaions for lower_64bit_integer_instructions() */
 #define MUL64                     (1U << 0)
 #define SIGN64                    (1U << 1)
+#define DIV64                     (1U << 2)
 
 /**
  * \see class lower_packing_builtins_visitor
index a12eba85c58d0759e2a17e1d260655410372114e..a0b5e1809a55081401e54f95c3af851ad21bd565 100644 (file)
@@ -368,6 +368,17 @@ lower_64bit_visitor::handle_rvalue(ir_rvalue **rvalue)
       }
       break;
 
+   case ir_binop_div:
+      if (lowering(DIV64)) {
+         if (ir->type->base_type == GLSL_TYPE_UINT64) {
+            *rvalue = handle_op(ir, "__builtin_udiv64", generate_ir::udiv64);
+         } else {
+            *rvalue = handle_op(ir, "__builtin_idiv64", generate_ir::idiv64);
+         }
+         this->progress = true;
+      }
+      break;
+
    case ir_binop_mul:
       if (lowering(MUL64)) {
          *rvalue = handle_op(ir, "__builtin_umul64", generate_ir::umul64);