Add space between -D and _ABC

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3604189754105ad519089eb58f07cdbe91a06e58..e9eccfc0e6a2af63cd4253fdfaed85fffbb271e8 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
        {
                if (check_label("begin")) {
                        if (vpr)
-                               run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+                               run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
                        else
-                               run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
+                               run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
 
                        run("read_verilog -lib +/xilinx/cells_xtra.v");