SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
extra : convert_revision :
b1ab34b7569db531cd1c74f273b24222e63f9007
# arch/alpha/alpha_tru64_process.cc
targetarch_files = Split('''
- alpha_common_syscall_emul.hh
alpha_linux_process.hh
alpha_memory.hh
alpha_tru64_process.hh
aout_machdep.h
arguments.hh
- byte_swap.hh
ecoff_machdep.h
ev5.hh
faults.hh
isa_fullsys_traits.hh
isa_traits.hh
- osfpal.hh
pseudo_inst.hh
stacktrace.hh
vptr.hh
vtophys.hh
''')
+# osfpal.hh
+# byte_swap.hh
+# alpha_common_syscall_emul.hh
# Set up bridging headers to the architecture specific versions
for f in targetarch_files:
build_dir = 'build/%s/' % env['BUILD_DIR'],
exports = 'env', duplicate = False)
+# Add a flag defining what THE_ISA should be for all compilation
+env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
+
# Set up complete list of sources based on configuration.
sources = base_sources + arch_source
env['TARGET_ISA'],
env['TARGET_ISA'])),
Split('''
- arch/%s/isa_desc
+ arch/%s/isa/main.isa
arch/isa_parser.py''' %
env['TARGET_ISA']),
'$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/%s' % env['TARGET_ISA'])
#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
#define __ARCH_ALPHA_ISA_TRAITS_HH__
+namespace LittleEndianGuest {}
+using namespace LittleEndianGuest;
+
#include "arch/alpha/faults.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
+//This makes sure the big endian versions of certain functions are used.
+namespace LittleEndianGuest {}
+using namespace LittleEndianGuest
+
#include "arch/mips/faults.hh"
#include "base/misc.hh"
#include "sim/host.hh"
#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
#define __ARCH_SPARC_ISA_TRAITS_HH__
+//This makes sure the big endian versions of certain functions are used.
+namespace BigEndianGuest {}
+using namespace BigEndianGuest;
+
#include "arch/sparc/faults.hh"
#include "base/misc.hh"
#include "sim/host.hh"
# value becomes sticky).
sticky_opts = Options(args=ARGUMENTS)
sticky_opts.AddOptions(
- EnumOption('TARGET_ISA', 'Target ISA', 'alpha', ('alpha', 'sparc')),
+ EnumOption('TARGET_ISA', 'Target ISA', 'alpha', ('alpha', 'sparc', 'mips')),
BoolOption('FULL_SYSTEM', 'Full-system support', False),
BoolOption('ALPHA_TLASER',
'Model Alpha TurboLaser platform (vs. Tsunami)', False),
#include "mem/mem_req.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
+#include "arch/isa_traits.hh"
#include "sim/byteswap.hh"
// forward declaration: see functional_memory.hh
#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
#include "cpu/o3/cpu.hh"
+#include "arch/isa_traits.hh"
+#include "sim/byteswap.hh"
template <class Impl>
class AlphaFullCPU : public FullO3CPU<Impl>
Fault error;
error = this->mem->read(req, data);
- data = LittleEndianGuest::gtoh(data);
+ data = gtoh(data);
return error;
}
#endif
- return this->mem->write(req, (T)LittleEndianGuest::htog(data));
+ return this->mem->write(req, (T)::htog(data));
}
template <class T>
// Remove this later; used only for debugging.
#define OPCODE(X) (X >> 26) & 0x3f
-
+#include "arch/isa_traits.hh"
#include "sim/byteswap.hh"
#include "cpu/exetrace.hh"
#include "mem/base_mem.hh"
assert(offset <= cacheBlkSize - instSize);
// Get the instruction from the array of the cache line.
- inst = LittleEndianGuest::gtoh(*reinterpret_cast<MachInst *>
+ inst = gtoh(*reinterpret_cast<MachInst *>
(&cacheData[offset]));
// Create a new DynInst from the instruction fetched.
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/builder.hh"
+#include "arch/isa_traits.hh"
#include "sim/byteswap.hh"
#include "targetarch/vtophys.hh"
uint8_t *ppc = physmem->dma_addr(ppc_paddr, sizeof(uint32_t));
uint8_t *timer = physmem->dma_addr(timer_paddr, sizeof(uint32_t));
- *(uint32_t *)ppc = LittleEndianGuest::htog((uint32_t)Clock::Frequency);
- *(uint32_t *)timer = LittleEndianGuest::htog((uint32_t)TIMER_FREQUENCY);
+ *(uint32_t *)ppc = htog((uint32_t)Clock::Frequency);
+ *(uint32_t *)timer = htog((uint32_t)TIMER_FREQUENCY);
}
#include "mem/functional/physical.hh"
#include "targetarch/vtophys.hh"
#include "sim/builder.hh"
+#include "arch/isa_traits.hh"
+#include "sim/byteswap.hh"
#include "sim/system.hh"
#include "base/trace.hh"
if (!hwrpb)
panic("could not translate hwrpb addr\n");
- *(uint64_t*)(hwrpb+0x50) = LittleEndianGuest::htog(params->system_type);
- *(uint64_t*)(hwrpb+0x58) = LittleEndianGuest::htog(params->system_rev);
+ *(uint64_t*)(hwrpb+0x50) = htog(params->system_type);
+ *(uint64_t*)(hwrpb+0x58) = htog(params->system_rev);
} else
panic("could not find hwrpb\n");
if (!m5AlphaAccess)
panic("could not translate m5AlphaAccess addr\n");
- *m5AlphaAccess = LittleEndianGuest::htog(EV5::Phys2K0Seg(access));
+ *m5AlphaAccess = htog(EV5::Phys2K0Seg(access));
} else
panic("could not find m5AlphaAccess\n");
}