#include "sim/debug.hh"
#include "sim/sim_exit.hh"
-using namespace AlphaISA;
+namespace AlphaISA {
#if FULL_SYSTEM
// Machine dependent functions
//
void
-AlphaISA::initCPU(ThreadContext *tc, int cpuId)
+initCPU(ThreadContext *tc, int cpuId)
{
initIPRs(tc, cpuId);
tc->setIntReg(16, cpuId);
tc->setIntReg(0, cpuId);
- AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
+ AlphaFault *reset = new ResetFault;
tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst));
template <class CPU>
void
-AlphaISA::processInterrupts(CPU *cpu)
+processInterrupts(CPU *cpu)
{
//Check if there are any outstanding interrupts
//Handle the interrupts
template <class CPU>
void
-AlphaISA::zeroRegisters(CPU *cpu)
+zeroRegisters(CPU *cpu)
{
// Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the
cpu->thread->setFloatReg(ZeroReg, 0.0);
}
-Fault
-SimpleThread::hwrei()
-{
- if (!(readPC() & 0x3))
- return new UnimplementedOpcodeFault;
-
- setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
-
- if (!misspeculating()) {
- if (kernelStats)
- kernelStats->hwrei();
- }
-
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
-}
-
int
-AlphaISA::MiscRegFile::getInstAsid()
+MiscRegFile::getInstAsid()
{
- return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+ return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
-AlphaISA::MiscRegFile::getDataAsid()
+MiscRegFile::getDataAsid()
{
- return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+ return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
#endif
//
//
void
-AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
+initIPRs(ThreadContext *tc, int cpuId)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
tc->setMiscRegNoEffect(i, 0);
}
- tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
+ tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
-AlphaISA::MiscReg
-AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
+MiscReg
+MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
uint64_t retval = 0; // return value, default 0
switch (idx) {
- case AlphaISA::IPR_PALtemp0:
- case AlphaISA::IPR_PALtemp1:
- case AlphaISA::IPR_PALtemp2:
- case AlphaISA::IPR_PALtemp3:
- case AlphaISA::IPR_PALtemp4:
- case AlphaISA::IPR_PALtemp5:
- case AlphaISA::IPR_PALtemp6:
- case AlphaISA::IPR_PALtemp7:
- case AlphaISA::IPR_PALtemp8:
- case AlphaISA::IPR_PALtemp9:
- case AlphaISA::IPR_PALtemp10:
- case AlphaISA::IPR_PALtemp11:
- case AlphaISA::IPR_PALtemp12:
- case AlphaISA::IPR_PALtemp13:
- case AlphaISA::IPR_PALtemp14:
- case AlphaISA::IPR_PALtemp15:
- case AlphaISA::IPR_PALtemp16:
- case AlphaISA::IPR_PALtemp17:
- case AlphaISA::IPR_PALtemp18:
- case AlphaISA::IPR_PALtemp19:
- case AlphaISA::IPR_PALtemp20:
- case AlphaISA::IPR_PALtemp21:
- case AlphaISA::IPR_PALtemp22:
- case AlphaISA::IPR_PALtemp23:
- case AlphaISA::IPR_PAL_BASE:
-
- case AlphaISA::IPR_IVPTBR:
- case AlphaISA::IPR_DC_MODE:
- case AlphaISA::IPR_MAF_MODE:
- case AlphaISA::IPR_ISR:
- case AlphaISA::IPR_EXC_ADDR:
- case AlphaISA::IPR_IC_PERR_STAT:
- case AlphaISA::IPR_DC_PERR_STAT:
- case AlphaISA::IPR_MCSR:
- case AlphaISA::IPR_ASTRR:
- case AlphaISA::IPR_ASTER:
- case AlphaISA::IPR_SIRR:
- case AlphaISA::IPR_ICSR:
- case AlphaISA::IPR_ICM:
- case AlphaISA::IPR_DTB_CM:
- case AlphaISA::IPR_IPLR:
- case AlphaISA::IPR_INTID:
- case AlphaISA::IPR_PMCTR:
+ case IPR_PALtemp0:
+ case IPR_PALtemp1:
+ case IPR_PALtemp2:
+ case IPR_PALtemp3:
+ case IPR_PALtemp4:
+ case IPR_PALtemp5:
+ case IPR_PALtemp6:
+ case IPR_PALtemp7:
+ case IPR_PALtemp8:
+ case IPR_PALtemp9:
+ case IPR_PALtemp10:
+ case IPR_PALtemp11:
+ case IPR_PALtemp12:
+ case IPR_PALtemp13:
+ case IPR_PALtemp14:
+ case IPR_PALtemp15:
+ case IPR_PALtemp16:
+ case IPR_PALtemp17:
+ case IPR_PALtemp18:
+ case IPR_PALtemp19:
+ case IPR_PALtemp20:
+ case IPR_PALtemp21:
+ case IPR_PALtemp22:
+ case IPR_PALtemp23:
+ case IPR_PAL_BASE:
+
+ case IPR_IVPTBR:
+ case IPR_DC_MODE:
+ case IPR_MAF_MODE:
+ case IPR_ISR:
+ case IPR_EXC_ADDR:
+ case IPR_IC_PERR_STAT:
+ case IPR_DC_PERR_STAT:
+ case IPR_MCSR:
+ case IPR_ASTRR:
+ case IPR_ASTER:
+ case IPR_SIRR:
+ case IPR_ICSR:
+ case IPR_ICM:
+ case IPR_DTB_CM:
+ case IPR_IPLR:
+ case IPR_INTID:
+ case IPR_PMCTR:
// no side-effect
retval = ipr[idx];
break;
- case AlphaISA::IPR_CC:
+ case IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
break;
- case AlphaISA::IPR_VA:
+ case IPR_VA:
retval = ipr[idx];
break;
- case AlphaISA::IPR_VA_FORM:
- case AlphaISA::IPR_MM_STAT:
- case AlphaISA::IPR_IFAULT_VA_FORM:
- case AlphaISA::IPR_EXC_MASK:
- case AlphaISA::IPR_EXC_SUM:
+ case IPR_VA_FORM:
+ case IPR_MM_STAT:
+ case IPR_IFAULT_VA_FORM:
+ case IPR_EXC_MASK:
+ case IPR_EXC_SUM:
retval = ipr[idx];
break;
- case AlphaISA::IPR_DTB_PTE:
+ case IPR_DTB_PTE:
{
- AlphaISA::TlbEntry &entry
+ TlbEntry &entry
= tc->getDTBPtr()->index(!tc->misspeculating());
retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
break;
// write only registers
- case AlphaISA::IPR_HWINT_CLR:
- case AlphaISA::IPR_SL_XMIT:
- case AlphaISA::IPR_DC_FLUSH:
- case AlphaISA::IPR_IC_FLUSH:
- case AlphaISA::IPR_ALT_MODE:
- case AlphaISA::IPR_DTB_IA:
- case AlphaISA::IPR_DTB_IAP:
- case AlphaISA::IPR_ITB_IA:
- case AlphaISA::IPR_ITB_IAP:
+ case IPR_HWINT_CLR:
+ case IPR_SL_XMIT:
+ case IPR_DC_FLUSH:
+ case IPR_IC_FLUSH:
+ case IPR_ALT_MODE:
+ case IPR_DTB_IA:
+ case IPR_DTB_IAP:
+ case IPR_ITB_IA:
+ case IPR_ITB_IAP:
panic("Tried to read write only register %d\n", idx);
break;
#endif
void
-AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
+MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
uint64_t old;
return;
switch (idx) {
- case AlphaISA::IPR_PALtemp0:
- case AlphaISA::IPR_PALtemp1:
- case AlphaISA::IPR_PALtemp2:
- case AlphaISA::IPR_PALtemp3:
- case AlphaISA::IPR_PALtemp4:
- case AlphaISA::IPR_PALtemp5:
- case AlphaISA::IPR_PALtemp6:
- case AlphaISA::IPR_PALtemp7:
- case AlphaISA::IPR_PALtemp8:
- case AlphaISA::IPR_PALtemp9:
- case AlphaISA::IPR_PALtemp10:
- case AlphaISA::IPR_PALtemp11:
- case AlphaISA::IPR_PALtemp12:
- case AlphaISA::IPR_PALtemp13:
- case AlphaISA::IPR_PALtemp14:
- case AlphaISA::IPR_PALtemp15:
- case AlphaISA::IPR_PALtemp16:
- case AlphaISA::IPR_PALtemp17:
- case AlphaISA::IPR_PALtemp18:
- case AlphaISA::IPR_PALtemp19:
- case AlphaISA::IPR_PALtemp20:
- case AlphaISA::IPR_PALtemp21:
- case AlphaISA::IPR_PALtemp22:
- case AlphaISA::IPR_PAL_BASE:
- case AlphaISA::IPR_IC_PERR_STAT:
- case AlphaISA::IPR_DC_PERR_STAT:
- case AlphaISA::IPR_PMCTR:
+ case IPR_PALtemp0:
+ case IPR_PALtemp1:
+ case IPR_PALtemp2:
+ case IPR_PALtemp3:
+ case IPR_PALtemp4:
+ case IPR_PALtemp5:
+ case IPR_PALtemp6:
+ case IPR_PALtemp7:
+ case IPR_PALtemp8:
+ case IPR_PALtemp9:
+ case IPR_PALtemp10:
+ case IPR_PALtemp11:
+ case IPR_PALtemp12:
+ case IPR_PALtemp13:
+ case IPR_PALtemp14:
+ case IPR_PALtemp15:
+ case IPR_PALtemp16:
+ case IPR_PALtemp17:
+ case IPR_PALtemp18:
+ case IPR_PALtemp19:
+ case IPR_PALtemp20:
+ case IPR_PALtemp21:
+ case IPR_PALtemp22:
+ case IPR_PAL_BASE:
+ case IPR_IC_PERR_STAT:
+ case IPR_DC_PERR_STAT:
+ case IPR_PMCTR:
// write entire quad w/ no side-effect
ipr[idx] = val;
break;
- case AlphaISA::IPR_CC_CTL:
+ case IPR_CC_CTL:
// This IPR resets the cycle counter. We assume this only
// happens once... let's verify that.
assert(ipr[idx] == 0);
ipr[idx] = 1;
break;
- case AlphaISA::IPR_CC:
+ case IPR_CC:
// This IPR only writes the upper 64 bits. It's ok to write
// all 64 here since we mask out the lower 32 in rpcc (see
// isa_desc).
ipr[idx] = val;
break;
- case AlphaISA::IPR_PALtemp23:
+ case IPR_PALtemp23:
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
#endif
break;
- case AlphaISA::IPR_DTB_PTE:
+ case IPR_DTB_PTE:
// write entire quad w/ no side-effect, tag is forthcoming
ipr[idx] = val;
break;
- case AlphaISA::IPR_EXC_ADDR:
+ case IPR_EXC_ADDR:
// second least significant bit in PC is always zero
ipr[idx] = val & ~2;
break;
- case AlphaISA::IPR_ASTRR:
- case AlphaISA::IPR_ASTER:
+ case IPR_ASTRR:
+ case IPR_ASTER:
// only write least significant four bits - privilege mask
ipr[idx] = val & 0xf;
break;
- case AlphaISA::IPR_IPLR:
+ case IPR_IPLR:
#ifdef DEBUG
if (break_ipl != -1 && break_ipl == (val & 0x1f))
debug_break();
#endif
break;
- case AlphaISA::IPR_DTB_CM:
+ case IPR_DTB_CM:
#if FULL_SYSTEM
if (val & 0x18) {
if (tc->getKernelStats())
- tc->getKernelStats()->mode(AlphaISA::Kernel::user, tc);
+ tc->getKernelStats()->mode(Kernel::user, tc);
} else {
if (tc->getKernelStats())
- tc->getKernelStats()->mode(AlphaISA::Kernel::kernel, tc);
+ tc->getKernelStats()->mode(Kernel::kernel, tc);
}
#endif
- case AlphaISA::IPR_ICM:
+ case IPR_ICM:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
- case AlphaISA::IPR_ALT_MODE:
+ case IPR_ALT_MODE:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
- case AlphaISA::IPR_MCSR:
+ case IPR_MCSR:
// more here after optimization...
ipr[idx] = val;
break;
- case AlphaISA::IPR_SIRR:
+ case IPR_SIRR:
// only write software interrupt mask
ipr[idx] = val & 0x7fff0;
break;
- case AlphaISA::IPR_ICSR:
+ case IPR_ICSR:
ipr[idx] = val & ULL(0xffffff0300);
break;
- case AlphaISA::IPR_IVPTBR:
- case AlphaISA::IPR_MVPTBR:
+ case IPR_IVPTBR:
+ case IPR_MVPTBR:
ipr[idx] = val & ULL(0xffffffffc0000000);
break;
- case AlphaISA::IPR_DC_TEST_CTL:
+ case IPR_DC_TEST_CTL:
ipr[idx] = val & 0x1ffb;
break;
- case AlphaISA::IPR_DC_MODE:
- case AlphaISA::IPR_MAF_MODE:
+ case IPR_DC_MODE:
+ case IPR_MAF_MODE:
ipr[idx] = val & 0x3f;
break;
- case AlphaISA::IPR_ITB_ASN:
+ case IPR_ITB_ASN:
ipr[idx] = val & 0x7f0;
break;
- case AlphaISA::IPR_DTB_ASN:
+ case IPR_DTB_ASN:
ipr[idx] = val & ULL(0xfe00000000000000);
break;
- case AlphaISA::IPR_EXC_SUM:
- case AlphaISA::IPR_EXC_MASK:
+ case IPR_EXC_SUM:
+ case IPR_EXC_MASK:
// any write to this register clears it
ipr[idx] = 0;
break;
- case AlphaISA::IPR_INTID:
- case AlphaISA::IPR_SL_RCV:
- case AlphaISA::IPR_MM_STAT:
- case AlphaISA::IPR_ITB_PTE_TEMP:
- case AlphaISA::IPR_DTB_PTE_TEMP:
+ case IPR_INTID:
+ case IPR_SL_RCV:
+ case IPR_MM_STAT:
+ case IPR_ITB_PTE_TEMP:
+ case IPR_DTB_PTE_TEMP:
// read-only registers
panic("Tried to write read only ipr %d\n", idx);
- case AlphaISA::IPR_HWINT_CLR:
- case AlphaISA::IPR_SL_XMIT:
- case AlphaISA::IPR_DC_FLUSH:
- case AlphaISA::IPR_IC_FLUSH:
+ case IPR_HWINT_CLR:
+ case IPR_SL_XMIT:
+ case IPR_DC_FLUSH:
+ case IPR_IC_FLUSH:
// the following are write only
ipr[idx] = val;
break;
- case AlphaISA::IPR_DTB_IA:
+ case IPR_DTB_IA:
// really a control write
ipr[idx] = 0;
tc->getDTBPtr()->flushAll();
break;
- case AlphaISA::IPR_DTB_IAP:
+ case IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
tc->getDTBPtr()->flushProcesses();
break;
- case AlphaISA::IPR_DTB_IS:
+ case IPR_DTB_IS:
// really a control write
ipr[idx] = val;
tc->getDTBPtr()->flushAddr(val,
- AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+ DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
break;
- case AlphaISA::IPR_DTB_TAG: {
- struct AlphaISA::TlbEntry entry;
+ case IPR_DTB_TAG: {
+ struct TlbEntry entry;
// FIXME: granularity hints NYI...
- if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
+ if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
+ entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
+ entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
+ entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
+ entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
+ entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
+ entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
+ entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
tc->getDTBPtr()->insert(val, entry);
}
break;
- case AlphaISA::IPR_ITB_PTE: {
- struct AlphaISA::TlbEntry entry;
+ case IPR_ITB_PTE: {
+ struct TlbEntry entry;
// FIXME: granularity hints NYI...
- if (AlphaISA::ITB_PTE_GH(val) != 0)
+ if (ITB_PTE_GH(val) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- entry.ppn = AlphaISA::ITB_PTE_PPN(val);
- entry.xre = AlphaISA::ITB_PTE_XRE(val);
+ entry.ppn = ITB_PTE_PPN(val);
+ entry.xre = ITB_PTE_XRE(val);
entry.xwe = 0;
- entry.fonr = AlphaISA::ITB_PTE_FONR(val);
- entry.fonw = AlphaISA::ITB_PTE_FONW(val);
- entry.asma = AlphaISA::ITB_PTE_ASMA(val);
- entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
+ entry.fonr = ITB_PTE_FONR(val);
+ entry.fonw = ITB_PTE_FONW(val);
+ entry.asma = ITB_PTE_ASMA(val);
+ entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
- tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
+ tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
}
break;
- case AlphaISA::IPR_ITB_IA:
+ case IPR_ITB_IA:
// really a control write
ipr[idx] = 0;
tc->getITBPtr()->flushAll();
break;
- case AlphaISA::IPR_ITB_IAP:
+ case IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
tc->getITBPtr()->flushProcesses();
break;
- case AlphaISA::IPR_ITB_IS:
+ case IPR_ITB_IS:
// really a control write
ipr[idx] = val;
tc->getITBPtr()->flushAddr(val,
- AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+ ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
break;
default:
void
-AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
+copyIprs(ThreadContext *src, ThreadContext *dest)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}
}
+} // namespace AlphaISA
+
#if FULL_SYSTEM
+using namespace AlphaISA;
+
+Fault
+SimpleThread::hwrei()
+{
+ if (!(readPC() & 0x3))
+ return new UnimplementedOpcodeFault;
+
+ setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
+
+ if (!misspeculating()) {
+ if (kernelStats)
+ kernelStats->hwrei();
+ }
+
+ // FIXME: XXX check for interrupts? XXX
+ return NoFault;
+}
/**
* Check for special simulator handling of specific PAL calls.
const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
const Addr VAddrUnImplMask = ~VAddrImplMask;
inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
-inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
-inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
+inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
+inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
addr |= PAddrUncachedBit40;
}
#endif
- return addr | AlphaISA::K0SegBase;
+ return addr | K0SegBase;
}
inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
inline Addr DTB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
+{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
inline Addr ITB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
+{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
-inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
-inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
+inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
+inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
const Addr PalBase = 0x4000;
const Addr PalMax = 0x10000;
// exception restart address
if (setRestartAddress() || !(tc->readPC() & 0x3))
- tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
+ tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
- tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
- tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
+ tc->setMiscRegNoEffect(IPR_EXC_ADDR,
+ tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
}
- tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
+ tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst));
}
if (!tc->misspeculating()
&& !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
// set VA register with faulting address
- tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
+ tc->setMiscRegNoEffect(IPR_VA, vaddr);
// set MM_STAT register flags
- tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
- (((AlphaISA::Opcode(tc->getInst()) & 0x3f) << 11)
- | ((AlphaISA::Ra(tc->getInst()) & 0x1f) << 6)
+ tc->setMiscRegNoEffect(IPR_MM_STAT,
+ (((Opcode(tc->getInst()) & 0x3f) << 11)
+ | ((Ra(tc->getInst()) & 0x1f) << 6)
| (flags & 0x3f)));
// set VA_FORM register with faulting formatted address
- tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
- tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
+ tc->setMiscRegNoEffect(IPR_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
}
AlphaFault::invoke(tc);
void ItbFault::invoke(ThreadContext * tc)
{
if (!tc->misspeculating()) {
- tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
- tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
- tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
- (AlphaISA::VAddr(pc).vpn() << 3));
+ tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+ tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_IVPTBR) |
+ (VAddr(pc).vpn() << 3));
}
AlphaFault::invoke(tc);
class DtbFault : public AlphaFault
{
protected:
- AlphaISA::VAddr vaddr;
+ VAddr vaddr;
uint32_t reqFlags;
uint64_t flags;
public:
- DtbFault(AlphaISA::VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
+ DtbFault(VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
: vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
{ }
FaultName name() const = 0;
static FaultVect _vect;
static FaultStat _count;
public:
- NDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ NDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
static FaultVect _vect;
static FaultStat _count;
public:
- PDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ PDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
static FaultVect _vect;
static FaultStat _count;
public:
- DtbPageFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ DtbPageFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
static FaultVect _vect;
static FaultStat _count;
public:
- DtbAcvFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ DtbAcvFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
static FaultVect _vect;
static FaultStat _count;
public:
- DtbAlignmentFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ DtbAlignmentFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
{
if (tc->getKernelStats())
tc->getKernelStats()->setIdleProcess(
- tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23), tc);
+ tc->readMiscRegNoEffect(IPR_PALtemp23), tc);
remove();
}
{
DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
- if (int_num < 0 || int_num >= AlphaISA::NumInterruptLevels)
+ if (int_num < 0 || int_num >= NumInterruptLevels)
panic("int_num out of bounds\n");
if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
namespace AlphaISA
{
#if FULL_SYSTEM
- const int reg_redir[AlphaISA::NumIntRegs] = {
+ const int reg_redir[NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
#else
- const int reg_redir[AlphaISA::NumIntRegs] = {
+ const int reg_redir[NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
/* Rb is a fake dependency so here is a fun way to get
* the parser to understand that.
*/
- Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0);
+ Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
#else
Ra = curTick;
0x00: CallPal::call_pal({{
if (!palValid ||
(palPriv
- && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
+ && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
// invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode
fault = new UnimplementedOpcodeFault;
bool dopal = xc->simPalCheck(palFunc);
if (dopal) {
- xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC);
- NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset;
+ xc->setMiscReg(IPR_EXC_ADDR, NPC);
+ NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
}
}
}}, IsNonSpeculative);
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (!AlphaISA::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
+ if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault;
}
return fault;
%(code)s;
} else {
m5_fesetround(getC99RoundingMode(
- xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
+ xc->readMiscRegNoEffect(MISCREG_FPCR)));
%(code)s;
m5_fesetround(M5_FE_TONEAREST);
}
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
- 'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
+ 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
'IsInteger', 1),
- 'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
+ 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
'IsInteger', 2),
- 'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
+ 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
'IsInteger', 3),
'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
void
Statistics::mode(cpu_mode newmode, ThreadContext *tc)
{
- Addr pcbb = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23);
+ Addr pcbb = tc->readMiscRegNoEffect(IPR_PALtemp23);
if (newmode == kernel && pcbb == idleProcess)
newmode = idle;
themode = (cpu_mode)exemode;
}
-} /* end namespace AlphaISA::Kernel */
-} /* end namespace AlphaISA */
+} // namespace Kernel
+} // namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string §ion);
};
-} /* end namespace AlphaISA::Kernel */
-} /* end namespace AlphaISA */
+} // namespace Kernel
+} // namespace AlphaISA
#endif // __ARCH_ALPHA_KERNEL_STATS_HH__
Addr offset() const { return addr & PageOffset; }
Addr level3() const
- { return AlphaISA::PteAddr(addr >> PageShift); }
+ { return PteAddr(addr >> PageShift); }
Addr level2() const
- { return AlphaISA::PteAddr(addr >> NPtePageShift + PageShift); }
+ { return PteAddr(addr >> NPtePageShift + PageShift); }
Addr level1() const
- { return AlphaISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+ { return PteAddr(addr >> 2 * NPtePageShift + PageShift); }
};
struct PageTableEntry
}
// Then loop through the floating point registers.
- for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
+ for (int i = 0; i < NumFloatRegs; ++i) {
dest->setFloatRegBits(i, src->readFloatRegBits(i));
}
void
copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR));
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ));
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG));
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR));
+ dest->setMiscRegNoEffect(MISCREG_FPCR,
+ src->readMiscRegNoEffect(MISCREG_FPCR));
+ dest->setMiscRegNoEffect(MISCREG_UNIQ,
+ src->readMiscRegNoEffect(MISCREG_UNIQ));
+ dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
+ src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
+ dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
+ src->readMiscRegNoEffect(MISCREG_LOCKADDR));
copyIprs(src, dest);
}
#else
Addr last_va;
- va = AlphaISA::TruncPage(va);
- last_va = AlphaISA::RoundPage(va + len);
+ va = TruncPage(va);
+ last_va = RoundPage(va + len);
do {
- if (AlphaISA::IsK0Seg(va)) {
- if (va < (AlphaISA::K0SegBase + pmem->size())) {
+ if (IsK0Seg(va)) {
+ if (va < (K0SegBase + pmem->size())) {
DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
"%#x < K0SEG + size\n", va);
return true;
* but there is no easy way to do it.
*/
- if (AlphaISA::PcPAL(va) || va < 0x10000)
+ if (PcPAL(va) || va < 0x10000)
return true;
- Addr ptbr = context->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
- AlphaISA::PageTableEntry pte = AlphaISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va);
+ Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
+ PageTableEntry pte = kernel_pte_lookup(context->getPhysPort(), ptbr, va);
if (!pte.valid()) {
DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
return false;
}
- va += AlphaISA::PageBytes;
+ va += PageBytes;
} while (va < last_va);
DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
gdbregs.regs[KGDB_REG_PC] = context->readPC();
// @todo: Currently this is very Alpha specific.
- if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) {
- for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) {
- gdbregs.regs[i] = context->readIntReg(AlphaISA::reg_redir[i]);
+ if (PcPAL(gdbregs.regs[KGDB_REG_PC])) {
+ for (int i = 0; i < NumIntArchRegs; ++i) {
+ gdbregs.regs[i] = context->readIntReg(reg_redir[i]);
}
} else {
- for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) {
+ for (int i = 0; i < NumIntArchRegs; ++i) {
gdbregs.regs[i] = context->readIntReg(i);
}
}
#ifdef KGDB_FP_REGS
- for (int i = 0; i < AlphaISA::NumFloatArchRegs; ++i) {
+ for (int i = 0; i < NumFloatArchRegs; ++i) {
gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i);
}
#endif
RemoteGDB::setregs()
{
// @todo: Currently this is very Alpha specific.
- if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) {
- for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) {
- context->setIntReg(AlphaISA::reg_redir[i], gdbregs.regs[i]);
+ if (PcPAL(gdbregs.regs[KGDB_REG_PC])) {
+ for (int i = 0; i < NumIntArchRegs; ++i) {
+ context->setIntReg(reg_redir[i], gdbregs.regs[i]);
}
} else {
- for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) {
+ for (int i = 0; i < NumIntArchRegs; ++i) {
context->setIntReg(i, gdbregs.regs[i]);
}
}
#ifdef KGDB_FP_REGS
- for (int i = 0; i < AlphaISA::NumFloatArchRegs; ++i) {
+ for (int i = 0; i < NumFloatArchRegs; ++i) {
context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]);
}
#endif
{
tc = _tc;
- bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+ bool usermode = (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
Addr pc = tc->readNextPC();
bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
}
SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
- Addr ksp = tc->readIntReg(AlphaISA::StackPointerReg);
+ Addr ksp = tc->readIntReg(StackPointerReg);
Addr bottom = ksp & ~0x3fff;
Addr addr;
bool
StackTrace::isEntry(Addr addr)
{
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12))
+ if (addr == tc->readMiscRegNoEffect(IPR_PALtemp12))
return true;
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7))
+ if (addr == tc->readMiscRegNoEffect(IPR_PALtemp7))
return true;
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11))
+ if (addr == tc->readMiscRegNoEffect(IPR_PALtemp11))
return true;
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21))
+ if (addr == tc->readMiscRegNoEffect(IPR_PALtemp21))
return true;
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9))
+ if (addr == tc->readMiscRegNoEffect(IPR_PALtemp9))
return true;
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2))
+ if (addr == tc->readMiscRegNoEffect(IPR_PALtemp2))
return true;
return false;
class StackTrace
{
- protected:
- typedef AlphaISA::MachInst MachInst;
private:
ThreadContext *tc;
std::vector<Addr> stack;
#include "params/AlphaSystem.hh"
#include "sim/byteswap.hh"
-
-using namespace LittleEndianGuest;
+using namespace AlphaISA;
AlphaSystem::AlphaSystem(Params *p)
: System(p)
// Load program sections into memory
- pal->loadSections(&functionalPort, AlphaISA::LoadAddrMask);
- console->loadSections(&functionalPort, AlphaISA::LoadAddrMask);
+ pal->loadSections(&functionalPort, LoadAddrMask);
+ console->loadSections(&functionalPort, LoadAddrMask);
// load symbols
if (!console->loadGlobalSymbols(consoleSymtab))
const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16);
uint32_t i1 = virtPort.read<uint32_t>(addr);
- uint32_t i2 = virtPort.read<uint32_t>(addr + sizeof(AlphaISA::MachInst));
+ uint32_t i2 = virtPort.read<uint32_t>(addr + sizeof(MachInst));
if ((i1 & inst_mask) == gp_ldah_pattern &&
(i2 & inst_mask) == gp_lda_pattern) {
- Addr new_addr = addr + 2* sizeof(AlphaISA::MachInst);
+ Addr new_addr = addr + 2* sizeof(MachInst);
DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr);
return new_addr;
} else {
{
Addr addr = 0;
if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
- virtPort.write(addr, htog(AlphaISA::Phys2K0Seg(access)));
+ virtPort.write(addr, htog(Phys2K0Seg(access)));
} else
panic("could not find m5AlphaAccess\n");
}
return *entry;
}
-/* end namespace AlphaISA */ }
+} // namespace AlphaISA
AlphaISA::ITB *
AlphaITBParams::create()
// static helper functions... really EV5 VM traits
static bool validVirtualAddress(Addr vaddr) {
// unimplemented bits must be all 0 or all 1
- Addr unimplBits = vaddr & AlphaISA::VAddrUnImplMask;
- return (unimplBits == 0) || (unimplBits == AlphaISA::VAddrUnImplMask);
+ Addr unimplBits = vaddr & VAddrUnImplMask;
+ return (unimplBits == 0) || (unimplBits == VAddrUnImplMask);
}
static Fault checkCacheability(RequestPtr &req, bool itb = false);
inline bool
inUserMode(ThreadContext *tc)
{
- return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+ return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
}
inline bool
#include "mem/vport.hh"
using namespace std;
-using namespace AlphaISA;
-AlphaISA::PageTableEntry
-AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
+namespace AlphaISA {
+
+PageTableEntry
+kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr)
{
Addr level1_pte = ptbr + vaddr.level1();
- AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
+ PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
if (!level1.valid()) {
DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
return 0;
}
Addr level2_pte = level1.paddr() + vaddr.level2();
- AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
+ PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
if (!level2.valid()) {
DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
return 0;
}
Addr level3_pte = level2.paddr() + vaddr.level3();
- AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
+ PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
if (!level3.valid()) {
DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
return 0;
}
Addr
-AlphaISA::vtophys(Addr vaddr)
+vtophys(Addr vaddr)
{
Addr paddr = 0;
- if (AlphaISA::IsUSeg(vaddr))
+ if (IsUSeg(vaddr))
DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- else if (AlphaISA::IsK0Seg(vaddr))
- paddr = AlphaISA::K0Seg2Phys(vaddr);
+ else if (IsK0Seg(vaddr))
+ paddr = K0Seg2Phys(vaddr);
else
panic("vtophys: ptbr is not set on virtual lookup");
}
Addr
-AlphaISA::vtophys(ThreadContext *tc, Addr addr)
+vtophys(ThreadContext *tc, Addr addr)
{
- AlphaISA::VAddr vaddr = addr;
- Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
+ VAddr vaddr = addr;
+ Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20);
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging?
- if (AlphaISA::PcPAL(vaddr) && (vaddr < AlphaISA::PalMax)) {
+ if (PcPAL(vaddr) && (vaddr < PalMax)) {
paddr = vaddr & ~ULL(1);
} else {
- if (AlphaISA::IsK0Seg(vaddr)) {
- paddr = AlphaISA::K0Seg2Phys(vaddr);
+ if (IsK0Seg(vaddr)) {
+ paddr = K0Seg2Phys(vaddr);
} else if (!ptbr) {
paddr = vaddr;
} else {
- AlphaISA::PageTableEntry pte =
+ PageTableEntry pte =
kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
if (pte.valid())
paddr = pte.paddr() | vaddr.offset();
return paddr;
}
+} // namespace AlphaISA
+
namespace AlphaISA {
PageTableEntry
- kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr);
+ kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr);
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
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