r200: fix indexed draw color order and cs missmatch

diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index e34ea9655e07ce6aa69ee21743f21b02f1f5b9e8..0487c3fcf59bee4f46457b6e762415fdc59969b6 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -137,6 +137,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
                BEGIN_BATCH(8+2);
                OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0);
                OUT_BATCH(R200_VF_PRIM_WALK_IND |
+                         R200_VF_COLOR_ORDER_RGBA | 
                          ((vertex_count + 0) << 16) |
                          type);
                
@@ -243,7 +244,7 @@ void r200EmitVertexAOS( r200ContextPtr rmesa,
              __FUNCTION__, vertex_size, offset);
 
 
-   BEGIN_BATCH(5);
+   BEGIN_BATCH(7);
    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2);
    OUT_BATCH(1);
    OUT_BATCH(vertex_size | (vertex_size << 8));

diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index be57ac3163877f32fe0adf6b72813a5ee2baa5b7..a71677909671a41d77b0984b7c4b1e763a961afc 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -295,12 +295,16 @@ VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 9
     h.i = hdr;                                                         \
     _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8);         \
     _sz = h.veclinear.count * 4;                                       \
+    if (r200->radeon.radeonScreen->kernel_mm && _sz) { \
+    BEGIN_BATCH_NO_AUTOSTATE(dwords); \
     OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0));               \
     OUT_BATCH(0);                                                      \
     OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0));             \
     OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));   \
     OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1));   \
     OUT_BATCH_TABLE((data), _sz);                                      \
+    END_BATCH(); \
+    } \
   } while(0)
 
 #define OUT_SCL(hdr, data) do {                                        \
@@ -367,9 +371,7 @@ static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    uint32_t dwords = atom->cmd_size;
 
    dwords += 4;
-   BEGIN_BATCH_NO_AUTOSTATE(dwords);
    OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
-   END_BATCH();
 }
 
 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)