;;- Machine description for GNU C compiler for Alliant FX systems
-;; Copyright (C) 1989, 1994 Free Software Foundation, Inc.
+;; Copyright (C) 1989, 1994, 1996 Free Software Foundation, Inc.
;; Adapted from m68k.md by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
;; and Joe Weening (weening@gang-of-four.stanford.edu).
;; Recognizers for btst instructions.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "di"))))]
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(match_operand:SI 1 "general_operand" "di"))))]
;; are automatically masked to 3 or 5 bits.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(and:SI
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(and:SI
;; Nonoffsettable mem refs are ok in this one pattern
;; since we don't try to adjust them.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "general_operand" "i")))]
"GET_CODE (operands[1]) == CONST_INT
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
(const_int 1)
(match_operand:SI 1 "general_operand" "i")))]
"GET_CODE (operands[1]) == CONST_INT"
;; which can usually be done with move instructions.
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "general_operand" "d"))]
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&d")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i")))]
"TARGET_68020 && TARGET_BITFIELD
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i")))]
"TARGET_68020 && TARGET_BITFIELD
;; "o,d" constraint causes a nonoffsettable memref to match the "o"
;; so that its address is reloaded.
-(define_insn "extv"
- [(set (match_operand:SI 0 "general_operand" "=d,d")
- (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
- (match_operand:SI 2 "general_operand" "di,di")
- (match_operand:SI 3 "general_operand" "di,di")))]
+(define_expand "extv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (sign_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=d")
+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
+ (match_operand:SI 2 "general_operand" "di")
+ (match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts [%c3,%c2]%1,%0")
-(define_insn "extzv"
- [(set (match_operand:SI 0 "general_operand" "=d,d")
- (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
- (match_operand:SI 2 "general_operand" "di,di")
- (match_operand:SI 3 "general_operand" "di,di")))]
+(define_expand "extzv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (zero_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=d")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
+ (match_operand:SI 2 "general_operand" "di")
+ (match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfextu [%c3,%c2]%1,%0")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
(match_operand:SI 3 "const_int_operand" "i,i")))]
"TARGET_68020 && TARGET_BITFIELD
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
"*
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
"*
return \"bfset [%c2,%c1]%0\";
}")
-(define_insn "insv"
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
- (match_operand:SI 3 "general_operand" "d,d"))]
+(define_expand "insv"
+ [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
+ (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" ""))
+ (match_operand:SI 3 "general_operand" ""))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
+ (match_operand:SI 3 "general_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
"bfins %3,[%c2,%c1]%0")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfextu [%c3,%c2]%1,%0")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 3 "general_operand" "d"))]
;;; now handle the register cases
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
+ (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
;;- Machine description for GNU compiler, Fujitsu Gmicro Version
-;; Copyright (C) 1990, 1994 Free Software Foundation, Inc.
+;; Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc.
;; Contributed by M.Yuhara, Fujitsu Laboratories LTD.
;; This file is part of GNU CC.
;; Recognizers for btst instructions.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "general_operand" "rmi")))]
""
"btst %1.w,%0.b")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "rm")
- (const_int 1)
- (match_operand:SI 1 "general_operand" "rmi")))]
- ""
- "btst %1.w,%0.h")
-
-(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "rmi")))]
""
;; are automatically masked to 3 or 5 bits when the base is a register.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "r")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(and:SI
(match_operand:SI 1 "general_operand" "rmi")
"btst %1.w,%0.b")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "r")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
(const_int 1)
(and:SI
(match_operand:SI 1 "general_operand" "rmi")
(define_insn ""
- [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "rm")))
+ [(set (cc0) (and:SI (sign_extend:SI
+ (sign_extend:HI
+ (match_operand:QI 0 "nonimmediate_operand" "rm")))
(match_operand:SI 1 "general_operand" "i")))]
"(GET_CODE (operands[1]) == CONST_INT
&& (unsigned) INTVAL (operands[1]) < 0x100
;; Should I add mode_dependent_address_p ????
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
(match_operand:SI 1 "immediate_operand" "i")
(match_operand:SI 2 "immediate_operand" "i"))
(match_operand:SI 3 "general_operand" "rm"))]
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&r")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "rm")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD
;; r.w m r.w/# rmi
;; %0 %1 %2 %3
-(define_insn "extv"
+(define_expand "extv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (sign_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_BITFIELD"
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
- (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:SI 2 "general_operand" "ri")
(match_operand:SI 3 "general_operand" "rmi")))]
"TARGET_BITFIELD"
"bfext %3,%2,%1,%0")
-(define_insn "extzv"
+(define_expand "extzv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (zero_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_BITFIELD"
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
- (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:SI 2 "general_operand" "ri")
(match_operand:SI 3 "general_operand" "rmi")))]
"TARGET_BITFIELD"
;; 0 1 2 3
-(define_insn "insv"
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+m,m")
+(define_expand "insv"
+ [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
+ (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" ""))
+ (match_operand:SI 3 "general_operand" ""))]
+ "TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m,m")
(match_operand:SI 1 "general_operand" "r,i")
(match_operand:SI 2 "general_operand" "rmi,i"))
(match_operand:SI 3 "general_operand" "ri,ri"))]
"TARGET_BITFIELD"
"bfinsu %3,%2,%1,%0")
+
;;; bfins/bfinsu ????????
;; == == == == == == == == == == == == ==
;;
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD"
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD"
;; GCC machine description for Intel X86.
-;; Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc.
+;; Copyright (C) 1988, 1994, 1995, 1996 Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; This file is part of GNU CC.
}
/* If we are loading a floating point constant that isn't 0 or 1
-into a register, indicate we need the pic register loaded. This could
-be optimized into stores of constants if the target eventually moves
-to memory, but better safe than sorry. */
+ into a register, indicate we need the pic register loaded. This could
+ be optimized into stores of constants if the target eventually moves
+ to memory, but better safe than sorry. */
if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) != MEM
&& GET_CODE (operands[1]) == CONST_DOUBLE
DONE;
}
- /* If we are loading a floating point constant that isn't 0 or 1 into a register,
- indicate we need the pic register loaded. This could be optimized into stores
- of constants if the target eventually moves to memory, but better safe than
- sorry. */
+ /* If we are loading a floating point constant that isn't 0 or 1 into a
+ register, indicate we need the pic register loaded. This could be
+ optimized into stores of constants if the target eventually moves to
+ memory, but better safe than sorry. */
if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) != MEM
&& GET_CODE (operands[1]) == CONST_DOUBLE
"* return output_move_memory (operands, insn, GET_MODE_SIZE (DFmode), 2, 4);")
;; For the purposes of regclass, prefer FLOAT_REGS.
-(define_insn "movdf_normal"
+(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
(match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
- "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+ "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
+ || (GET_CODE (operands[1]) != MEM)"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
}
/* If we are loading a floating point constant that isn't 0 or 1
-into a register, indicate we need the pic register loaded. This could
-be optimized into stores of constants if the target eventually moves
-to memory, but better safe than sorry. */
+ into a register, indicate we need the pic register loaded. This could
+ be optimized into stores of constants if the target eventually moves
+ to memory, but better safe than sorry. */
if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) != MEM
&& GET_CODE (operands[1]) == CONST_DOUBLE
""
"* return output_move_memory (operands, insn, GET_MODE_SIZE (XFmode), 2, 4);")
-(define_insn "movxf_normal"
+(define_insn ""
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
(match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
- "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+ "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
+ || (GET_CODE (operands[1]) != MEM)"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
;; This usually looses. But try a define_expand to recognize a few case
;; we can do efficiently, such as accessing the "high" QImode registers,
;; %ah, %bh, %ch, %dh.
+;; ??? Note this has a botch on the mode of operand 0, which needs to be
+;; fixed if this is ever enabled.
(define_insn "insv"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r")
(match_operand:SI 1 "immediate_operand" "i")
FAIL;
}")
-;; ??? Are these constraints right?
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+&qo")
- (const_int 8)
- (const_int 8))
- (match_operand:QI 1 "general_operand" "qn"))]
- ""
- "*
-{
- if (REG_P (operands[0]))
- return AS2 (mov%B0,%1,%h0);
-
- operands[0] = adj_offsettable_operand (operands[0], 1);
- return AS2 (mov%B0,%1,%0);
-}")
-*/
-
;; On i386, the register count for a bit operation is *not* truncated,
;; so SHIFT_COUNT_TRUNCATED must not be defined.
;; General bit set and clear.
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
(const_int 1)
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 3 "const_int_operand" "n"))]
;; The CPU may access unspecified bytes around the actual target byte.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n")))]
"GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
;; Recognizers for btst instructions.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "di"))))]
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(match_operand:SI 1 "general_operand" "di"))))]
;; are automatically masked to 3 or 5 bits.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(and:SI
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(and:SI
;; Nonoffsettable mem refs are ok in this one pattern
;; since we don't try to adjust them.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
"(unsigned) INTVAL (operands[1]) < 8"
}")
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
""
; than an odd byte aligned bit field instruction.
;
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o")
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(const_int 32)
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "general_operand" "rmi"))]
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "register_operand" "d"))]
;
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=rm")
- (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
(const_int 32)
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&d")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
;
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=rm")
- (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
(const_int 32)
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
;; "o,d" constraint causes a nonoffsettable memref to match the "o"
;; so that its address is reloaded.
-(define_insn "extv"
- [(set (match_operand:SI 0 "general_operand" "=d,d")
- (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
- (match_operand:SI 2 "general_operand" "di,di")
- (match_operand:SI 3 "general_operand" "di,di")))]
+(define_expand "extv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (sign_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=d")
+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
+ (match_operand:SI 2 "general_operand" "di")
+ (match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts %1{%b3:%b2},%0")
-(define_insn "extzv"
+(define_expand "extzv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (zero_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d,d")
- (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
(match_operand:SI 2 "general_operand" "di,di")
(match_operand:SI 3 "general_operand" "di,di")))]
"TARGET_68020 && TARGET_BITFIELD"
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
- (match_operand 3 "const_int_operand" "n,n")))]
+ (match_operand 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
&& (INTVAL (operands[3]) == -1
|| (GET_CODE (operands[1]) == CONST_INT
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
"*
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
"*
return \"bfset %0{%b2:%b1}\";
}")
-(define_insn "insv"
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
- (match_operand:SI 1 "general_operand" "di,di")
- (match_operand:SI 2 "general_operand" "di,di"))
- (match_operand:SI 3 "register_operand" "d,d"))]
+(define_expand "insv"
+ [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
+ (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" ""))
+ (match_operand:SI 3 "register_operand" ""))]
+ "TARGET_68020 && TARGET_BITFIELD"
+ "")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+ (match_operand:SI 1 "general_operand" "di")
+ (match_operand:SI 2 "general_operand" "di"))
+ (match_operand:SI 3 "register_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
"bfins %3,%0{%b2:%b1}")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
}")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 3 "register_operand" "d"))]
;;; now handle the register cases
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
+ (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
;; Machine description for GNU compiler, Tahoe version
-;; Copyright (C) 1989, 1994 Free Software Foundation, Inc.
+;; Copyright (C) 1989, 1994, 1996 Free Software Foundation, Inc.
;; This file is part of GNU CC.
(define_insn ""
[(set (pc)
(if_then_else
- (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
;;- Machine description for GNU compiler, Vax Version
-;; Copyright (C) 1987, 1988, 1991, 1994, 1995 Free Software Foundation, Inc.
+;; Copyright (C) 1987, 88, 91, 94, 95, 1996 Free Software Foundation, Inc.
;; This file is part of GNU CC.
;; which can usually be done with move instructions.
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
(match_operand:QI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "general_operand" "g"))]
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&g")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
(define_insn ""
[(set (cc0)
(compare
- (sign_extract:SI (match_operand:SI 0 "nonmemory_operand" "r")
+ (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g")))]
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
- (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
+ (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
- (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
(define_insn ""
[(set (cc0)
(compare
- (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
+ (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g")))]
(define_insn "extv"
[(set (match_operand:SI 0 "general_operand" "=g")
- (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
}")
-(define_insn "extzv"
+(define_expand "extzv"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (zero_extract:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:QI 2 "general_operand" "")
+ (match_operand:SI 3 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
- (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
}")
-(define_insn "insv"
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+g")
+(define_expand "insv"
+ [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
+ (match_operand:QI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" ""))
+ (match_operand:SI 3 "general_operand" ""))]
+ ""
+ "")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g"))]
"insv %3,%2,%1,%0")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+r")
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g"))]
(define_insn ""
[(set (pc)
(if_then_else
- (ne (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
+ (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
(const_int 1)
(match_operand:SI 1 "general_operand" "I,g"))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (eq (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
+ (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
(const_int 1)
(match_operand:SI 1 "general_operand" "I,g"))
(const_int 0))