soc/interconnect/stream: fix specific cases for last/first signal in UpConverter

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index bc6793cacca2e41a807595911355f1d900518182..fea05b43e7b5b46619442ee28b166b551adbc2c7 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -176,8 +176,13 @@ class _UpConverter(Module):
                 )
             ),
             If(source.valid & source.ready,
-                source.first.eq(sink.first),
-                source.last.eq(sink.last),
+                If(sink.valid & sink.ready,
+                    source.first.eq(sink.first),
+                    source.last.eq(sink.last)
+                ).Else(
+                    source.first.eq(0),
+                    source.last.eq(0)
+                )
             ).Elif(sink.valid & sink.ready,
                 source.first.eq(sink.first | source.first),
                 source.last.eq(sink.last | source.last)