from m5.objects.Gic import ArmPPI
from m5.objects.Iris import IrisBaseCPU
from m5.objects.SystemC import SystemC_ScModule
+from m5.util.fdthelper import FdtNode, FdtPropertyWords
class FastModelCortexA76(IrisBaseCPU):
type = 'FastModelCortexA76'
walk_cache_latency = Param.UInt64(0, "Walk cache latency for TA (Timing "\
"Annotation), expressed in simulation ticks")
+ def generateDeviceTree(self, state):
+ node = FdtNode("timer")
+
+ node.appendCompatible(["arm,cortex-a15-timer",
+ "arm,armv7-timer",
+ "arm,armv8-timer"])
+ node.append(FdtPropertyWords("interrupts", [
+ 1, int(self.cntpsirq.num), 0xf08,
+ 1, int(self.cntpnsirq.num), 0xf08,
+ 1, int(self.cntvirq.num), 0xf08,
+ 1, int(self.cnthpirq.num), 0xf08,
+ ]))
+
+ yield node
+
class FastModelScxEvsCortexA76x1(SystemC_ScModule):
type = 'FastModelScxEvsCortexA76x1'
cxx_class = 'FastModel::ScxEvsCortexA76<FastModel::ScxEvsCortexA76x1Types>'
from m5.objects.FastModelGIC import FastModelGIC, SCFastModelGIC
from m5.objects.Gic import ArmSPI
from m5.objects.RealView import VExpress_GEM5_Base, HDLcd
+from m5.objects.SubSystem import SubSystem
class VExpressFastmodel(VExpress_GEM5_Base):
gic = FastModelGIC(
pxl_clk=VExpress_GEM5_Base.dcc.osc_pxl, pio_addr=0x2b000000,
interrupt=ArmSPI(num=95))
- def __init__(self, *args, **kwargs):
- super(VExpressFastmodel, self).__init__(*args, **kwargs)
+ # Remove original timer to prevent from possible conflict with Fastmodel
+ # timer.
+ generic_timer = SubSystem()
+ generic_timer_mem = SubSystem()
+ sys_counter = SubSystem()
def _on_chip_devices(self):
- devices = super(VExpressFastmodel, self)._on_chip_devices()
- devices += [ self.gic, self.hdlcd ]
- devices.remove(self.generic_timer)
- return devices
+ return [
+ self.gic,
+ self.hdlcd,
+ self.system_watchdog,
+ self.trusted_watchdog,
+ ]
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None: