ac: compute the DCC fast clear size per slice on GFX8

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 9e45bd44b726c0b1164c800b1878a28e33896402..55237eb1eef59d55e17f7e0232a1ed124640ab8c 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -308,6 +308,33 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
                         * slice is the same size) it's easy to compute.
                         */
                        surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
+
+                       /* For arrays, we have to compute the DCC info again
+                        * with one slice size to get a correct fast clear
+                        * size.
+                        */
+                       if (config->info.array_size > 1) {
+                               AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
+                               AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
+                               AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
+                               AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
+                               AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
+
+                               ret = AddrComputeDccInfo(addrlib,
+                                                        AddrDccIn, AddrDccOut);
+                               if (ret == ADDR_OK) {
+                                       /* If the DCC memory isn't properly
+                                        * aligned, the data are interleaved
+                                        * accross slices.
+                                        */
+                                       if (AddrDccOut->dccRamSizeAligned)
+                                               surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
+                                       else
+                                               surf_level->dcc_slice_fast_clear_size = 0;
+                               }
+                       } else {
+                               surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
+                       }
                }
        }
 

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 8143c9f9a0e8523c860a8c69e9c7723b1ea2ba00..a4144a4e16cbc82b28938124b93e7d3051ddb1ad 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -76,6 +76,7 @@ struct legacy_surf_level {
     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
     uint32_t                    dcc_fast_clear_size;
+    uint32_t                    dcc_slice_fast_clear_size;
     unsigned                    nblk_x:15;
     unsigned                    nblk_y:15;
     enum radeon_surf_mode       mode:2;