add in use of SVSHAPE in ISACaller. untested (no damage done)

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index fb17a1f271d1e535a01b34d5d586bbba51052ae7..40e5ef28b95aadc72e01f49945d7e21c2753fd5e 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1196,6 +1196,39 @@ class ISACaller:
                                        self.namespace['NIA'])
             return
 
+        # for when SVSHAPE is active, a very bad hack here (to be replaced)
+        # using pre-arranged schedule.  all of this is awful but it is a
+        # start.  next job will be to put the proper activation in place
+        yield self.dec2.remap_active.eq(self.last_op_svshape)
+        if self.last_op_svshape:
+            # get four SVSHAPEs. here we are hard-coding
+            # SVSHAPE0 to FRT, SVSHAPE1 to FRA, SVSHAPE2 to FRC and
+            # SVSHAPE3 to FRB, assuming "fmadd FRT, FRA, FRC, FRB."
+            remaps = [self.spr['SVSHAPE0'].get_iterator(),
+                      self.spr['SVSHAPE1'].get_iterator(),
+                      self.spr['SVSHAPE2'].get_iterator(),
+                      self.spr['SVSHAPE3'].get_iterator(),
+                     ]
+            for i, remap in enumerate(remaps):
+                # XXX hardcoded! pick dststep for out (i==0) else srcstep
+                step = dststep if (i == 0) else srcstep
+                # this is terrible.  O(N^2) looking for the match. but hey.
+                for idx, remap_idx in remap:
+                    if idx == step:
+                        break
+                if i == 0:
+                    yield self.dec2.o_step.eq(step)
+                    yield self.dec2.o2_step.eq(step)
+                elif i == 1:
+                    yield self.dec2.in1_step.eq(step)
+                elif i == 2:
+                    yield self.dec2.in2_step.eq(step)
+                elif i == 3:
+                    yield self.dec2.in3_step.eq(step)
+        # after that, settle down (combinatorial) to let Vector reg numbers
+        # work themselves out
+        yield Settle()
+
         # main input registers (RT, RA ...)
         inputs = []
         for name in input_names:

diff --git a/src/openpower/decoder/isa/svshape.py b/src/openpower/decoder/isa/svshape.py
index 139b540d260f7553fb40ff1e29d5b56de87b547e..16f90a0ad2c455031a82f51e24102322fb486c8f 100644 (file)
--- a/src/openpower/decoder/isa/svshape.py
+++ b/src/openpower/decoder/isa/svshape.py
@@ -3,6 +3,8 @@ from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from openpower.sv.svp64 import SVP64REMAP
 import os
+from copy import deepcopy
+
 
 class SVSHAPE(SelectableInt):
     def __init__(self, value):
@@ -76,7 +78,8 @@ class SVSHAPE(SelectableInt):
         self.fsi['offset'].eq(value)
 
     def get_iterator(self):
-        return iterate_indices(self)
+        # create a **NEW** iterator each time this is called
+        return iterate_indices(deepcopy(self))
 
 
 if __name__ == '__main__':