Add PCI IDs for the G33, Q33, and Q35 chipsets.
authorWang Zhenyu <zhenyu.z.wang@intel.com>
Tue, 5 Jun 2007 18:42:43 +0000 (11:42 -0700)
committerEric Anholt <eric@anholt.net>
Tue, 5 Jun 2007 19:01:28 +0000 (12:01 -0700)
src/mesa/drivers/dri/i915/i915_texstate.c
src/mesa/drivers/dri/i915/intel_context.c
src/mesa/drivers/dri/i915/intel_context.h
src/mesa/drivers/dri/i915/intel_screen.c
src/mesa/drivers/dri/i915/intel_tex.c
src/mesa/drivers/dri/i915tex/intel_context.c
src/mesa/drivers/dri/i915tex/intel_context.h
src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c
src/mesa/drivers/dri/i915tex/intel_screen.c

index d0e8474b449505dd9fbba4431519a9f8a2e84161..a19d4b65840a330e0bac03bdbe77017ebfafffd2 100644 (file)
@@ -491,13 +491,19 @@ static void i915SetTexImages( i915ContextPtr i915,
       abort();
    }
 
-
-   if (i915->intel.intelScreen->deviceID == PCI_CHIP_I945_G ||
-       i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM ||
-       i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GME)
-      i945LayoutTextureImages( i915, tObj );    
-   else
-      i915LayoutTextureImages( i915, tObj );
+   switch (i915->intel.intelScreen->deviceID) {
+   case PCI_CHIP_I945_G:
+   case PCI_CHIP_I945_GM:
+   case PCI_CHIP_I945_GME:
+   case PCI_CHIP_G33_G:
+   case PCI_CHIP_Q33_G:
+   case PCI_CHIP_Q35_G:
+       i945LayoutTextureImages( i915, tObj );
+       break;
+   default:
+       i915LayoutTextureImages( i915, tObj );
+       break;
+   }
 
    t->Setup[I915_TEXREG_MS3] = 
       (((tObj->Image[0][t->intel.base.firstLevel]->Height - 1) << MS3_HEIGHT_SHIFT) |
index 9f25b099b11e92d0bbf10244445b2ad5b6ed03a0..11c23f24a1b8538d1c496f3b3223b35165605d89 100644 (file)
@@ -125,6 +125,12 @@ const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
         chipset = "Intel(R) 945GM"; break;
       case PCI_CHIP_I945_GME:
         chipset = "Intel(R) 945GME"; break;
+      case PCI_CHIP_G33_G:
+        chipset = "Intel(R) G33"; break;
+      case PCI_CHIP_Q35_G:
+        chipset = "Intel(R) Q35"; break;
+      case PCI_CHIP_Q33_G:
+        chipset = "Intel(R) Q33"; break;
       default:
         chipset = "Unknown Intel Chipset"; break;
       }
index ae05145a56b054492ba9f6c780fd2c8e5f929953..3b50107d73f91807ea511451a078a3b1b2ff4932 100644 (file)
@@ -455,6 +455,9 @@ extern int INTEL_DEBUG;
 #define PCI_CHIP_I945_G                        0x2772
 #define PCI_CHIP_I945_GM               0x27A2
 #define PCI_CHIP_I945_GME              0x27AE
+#define PCI_CHIP_G33_G                 0x29C2
+#define PCI_CHIP_Q35_G                 0x29B2
+#define PCI_CHIP_Q33_G                 0x29D2
 
 
 /* ================================================================
index d6c1cfe6565249a06aa12b49bc6d89942146d938..ca8610b4965ff8084919b87de7bf15931104cd17 100644 (file)
@@ -515,6 +515,9 @@ static GLboolean intelCreateContext( const __GLcontextModes *mesaVis,
    case PCI_CHIP_I945_G:
    case PCI_CHIP_I945_GM:
    case PCI_CHIP_I945_GME:
+   case PCI_CHIP_G33_G:
+   case PCI_CHIP_Q35_G:
+   case PCI_CHIP_Q33_G:
       return i915CreateContext( mesaVis, driContextPriv, 
                               sharedContextPrivate );
  
index d75ebd8ffcfe58309a68b2387f3e256b3da8f392..5bd280652afb0939a6d690bc38f70522fb584d35 100644 (file)
@@ -678,7 +678,10 @@ static void intelUploadTexImage( intelContextPtr intel,
     */
    else if (intel->intelScreen->deviceID == PCI_CHIP_I945_G ||
             intel->intelScreen->deviceID == PCI_CHIP_I945_GM ||
-            intel->intelScreen->deviceID == PCI_CHIP_I945_GME) {
+            intel->intelScreen->deviceID == PCI_CHIP_I945_GME ||
+            intel->intelScreen->deviceID == PCI_CHIP_G33_G ||
+            intel->intelScreen->deviceID == PCI_CHIP_Q33_G ||
+            intel->intelScreen->deviceID == PCI_CHIP_Q35_G) {
       GLuint row_len = image->Width * image->TexFormat->TexelBytes;
       GLubyte *dst = (GLubyte *)(t->BufAddr + offset);
       GLubyte *src = (GLubyte *)image->Data;
index e581cb080b94f339801454092f0163bb9b8b8869..c927dca8e5aab4f7f40c808044ed10fc2c074814 100644 (file)
@@ -133,6 +133,15 @@ intelGetString(GLcontext * ctx, GLenum name)
       case PCI_CHIP_I945_GME:
          chipset = "Intel(R) 945GME";
          break;
+      case PCI_CHIP_G33_G:
+        chipset = "Intel(R) G33";
+        break;
+      case PCI_CHIP_Q35_G:
+        chipset = "Intel(R) Q35";
+        break;
+      case PCI_CHIP_Q33_G:
+        chipset = "Intel(R) Q33";
+        break;
       default:
          chipset = "Unknown Intel Chipset";
          break;
index 24e2b37e0bf044b3e733cb1ff4a6d6153c2a3969..9d060eb866f7e70be411f13626ba6b790e268294 100644 (file)
@@ -386,6 +386,9 @@ extern int INTEL_DEBUG;
 #define PCI_CHIP_I945_G                        0x2772
 #define PCI_CHIP_I945_GM               0x27A2
 #define PCI_CHIP_I945_GME              0x27AE
+#define PCI_CHIP_G33_G                 0x29C2
+#define PCI_CHIP_Q35_G                 0x29B2
+#define PCI_CHIP_Q33_G                 0x29D2
 
 
 /* ================================================================
index 9e90dd16c1de4f0089550754724de7854b970694..843a78eb82b44d78753a88b3210715d835a1aeeb 100644 (file)
@@ -80,6 +80,9 @@ intel_miptree_create(struct intel_context *intel,
    case PCI_CHIP_I945_G:
    case PCI_CHIP_I945_GM:
    case PCI_CHIP_I945_GME:
+   case PCI_CHIP_G33_G:
+   case PCI_CHIP_Q33_G:
+   case PCI_CHIP_Q35_G:
       ok = i945_miptree_layout(mt);
       break;
    case PCI_CHIP_I915_G:
index 5840d6297e731aa71112a4ae7a778591d31a2d7e..2acdead63d5d02207c820a2499add5b1e3d0a559 100644 (file)
@@ -753,6 +753,9 @@ intelCreateContext(const __GLcontextModes * mesaVis,
    case PCI_CHIP_I945_G:
    case PCI_CHIP_I945_GM:
    case PCI_CHIP_I945_GME:
+   case PCI_CHIP_G33_G:
+   case PCI_CHIP_Q35_G:
+   case PCI_CHIP_Q33_G:
       return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate);
 
    default: