abort();
}
-
- if (i915->intel.intelScreen->deviceID == PCI_CHIP_I945_G ||
- i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM ||
- i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GME)
- i945LayoutTextureImages( i915, tObj );
- else
- i915LayoutTextureImages( i915, tObj );
+ switch (i915->intel.intelScreen->deviceID) {
+ case PCI_CHIP_I945_G:
+ case PCI_CHIP_I945_GM:
+ case PCI_CHIP_I945_GME:
+ case PCI_CHIP_G33_G:
+ case PCI_CHIP_Q33_G:
+ case PCI_CHIP_Q35_G:
+ i945LayoutTextureImages( i915, tObj );
+ break;
+ default:
+ i915LayoutTextureImages( i915, tObj );
+ break;
+ }
t->Setup[I915_TEXREG_MS3] =
(((tObj->Image[0][t->intel.base.firstLevel]->Height - 1) << MS3_HEIGHT_SHIFT) |
chipset = "Intel(R) 945GM"; break;
case PCI_CHIP_I945_GME:
chipset = "Intel(R) 945GME"; break;
+ case PCI_CHIP_G33_G:
+ chipset = "Intel(R) G33"; break;
+ case PCI_CHIP_Q35_G:
+ chipset = "Intel(R) Q35"; break;
+ case PCI_CHIP_Q33_G:
+ chipset = "Intel(R) Q33"; break;
default:
chipset = "Unknown Intel Chipset"; break;
}
#define PCI_CHIP_I945_G 0x2772
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
+#define PCI_CHIP_G33_G 0x29C2
+#define PCI_CHIP_Q35_G 0x29B2
+#define PCI_CHIP_Q33_G 0x29D2
/* ================================================================
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
+ case PCI_CHIP_G33_G:
+ case PCI_CHIP_Q35_G:
+ case PCI_CHIP_Q33_G:
return i915CreateContext( mesaVis, driContextPriv,
sharedContextPrivate );
*/
else if (intel->intelScreen->deviceID == PCI_CHIP_I945_G ||
intel->intelScreen->deviceID == PCI_CHIP_I945_GM ||
- intel->intelScreen->deviceID == PCI_CHIP_I945_GME) {
+ intel->intelScreen->deviceID == PCI_CHIP_I945_GME ||
+ intel->intelScreen->deviceID == PCI_CHIP_G33_G ||
+ intel->intelScreen->deviceID == PCI_CHIP_Q33_G ||
+ intel->intelScreen->deviceID == PCI_CHIP_Q35_G) {
GLuint row_len = image->Width * image->TexFormat->TexelBytes;
GLubyte *dst = (GLubyte *)(t->BufAddr + offset);
GLubyte *src = (GLubyte *)image->Data;
case PCI_CHIP_I945_GME:
chipset = "Intel(R) 945GME";
break;
+ case PCI_CHIP_G33_G:
+ chipset = "Intel(R) G33";
+ break;
+ case PCI_CHIP_Q35_G:
+ chipset = "Intel(R) Q35";
+ break;
+ case PCI_CHIP_Q33_G:
+ chipset = "Intel(R) Q33";
+ break;
default:
chipset = "Unknown Intel Chipset";
break;
#define PCI_CHIP_I945_G 0x2772
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
+#define PCI_CHIP_G33_G 0x29C2
+#define PCI_CHIP_Q35_G 0x29B2
+#define PCI_CHIP_Q33_G 0x29D2
/* ================================================================
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
+ case PCI_CHIP_G33_G:
+ case PCI_CHIP_Q33_G:
+ case PCI_CHIP_Q35_G:
ok = i945_miptree_layout(mt);
break;
case PCI_CHIP_I915_G:
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
+ case PCI_CHIP_G33_G:
+ case PCI_CHIP_Q35_G:
+ case PCI_CHIP_Q33_G:
return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate);
default: