# ULX3S JTAG Connection with STLINKV2
Cross referenced with:
-https://bugs.libre-soc.org/show_bug.cgi?id=517
-http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html
-lkcl:
-```
-the JTAG TAP interface on the *FPGA* is hard-coded silicon.
-
-the JTAG TAP interface connected on the processor and soft-implemented
-*by* the FPGA is likely completely inaccessible until someone
-allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config.
-
-which means: someone's going to have to to through this file:
-https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/ulx3s.py#L72
-(which defines the pin allocations)
-
-and in this file do some Voodoo Magic on this file's TestSoC:
-https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ulx3s85f.py;hb=HEAD
-
-similar to these four lines:
-https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=4279effcffe2fbf15f877e9b2a1b76beab248dac;hb=HEAD#l460
+<https://bugs.libre-soc.org/show_bug.cgi?id=517>
-but instead doing something like... err....
-gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py
-there's gpio 0, 1, and 2
-self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back
-in that file there are 2 pins, one named "p", one named "n"
-self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc.
+<http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
-and then request gpio1 for the other 2 pins
-
-theeeen you'll need to go back to that ulx3s.py litex platform file,
-look up the pin names B11, C11, A10, A11, and find out what the hell
-they are, whether they're suitable for use.
-
-if they are, then great! these are what you wire up the STLINKv2 to,
-according to what you decided to connect to just above.
-
-but for god's sake do not get this wrong, such as driving an input as
-an output or vice-versa, or wiring up 5.0V to GND with those
-jumper-cables.
-
-do *NOT* randomly upload and power up the ulx3s until this has been
-THOROUGHLY triple-checked. or, you are entirely free to not bother
-and to end up learning the hard way by destroying the FPGA.
-```
+## Original Instructions
-Connecting the dots:
-
-litex platform file litex-boards/litex_boards/platforms/ulx3s.py
-
-("gpio", 0,
- Subsignal("p", Pins("B11")),
- Subsignal("n", Pins("C11")),
- IOStandard("LVCMOS33")
-),
-("gpio", 1,
- Subsignal("p", Pins("A10")),
- Subsignal("n", Pins("A11")),
- IOStandard("LVCMOS33")
-),
-
-ULX3S FPGA constraints file github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342
+lkcl:
-LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK
-LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK
-LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK
-LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK
-ULX3S FPGA Schematic https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
+> the JTAG TAP interface on the *FPGA* is hard-coded silicon.
+
+> the JTAG TAP interface connected on the processor and soft-implemented
+> *by* the FPGA is likely completely inaccessible until someone
+> allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config.
+>
+> which means: someone's going to have to to through this file:
+> <https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/ulx3s.py#L72>
+> (which defines the pin allocations)
+>
+> and in this file do some Voodoo Magic on this file's TestSoC:
+> <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ulx3s85f.py;hb=HEAD>
+>
+> similar to these four lines:
+> <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=4279effcffe2fbf15f877e9b2a1b76beab248dac;hb=HEAD#l460>
+>
+> but instead doing something like... err....
+>
+> gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py there's gpio 0, 1, and 2
+>
+> self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back in that file there are 2 pins, one named "p", one named "n"
+>
+> self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc.
+>
+> and then request gpio1 for the other 2 pins
+>
+> theeeen you'll need to go back to that ulx3s.py litex platform file,
+> look up the pin names B11, C11, A10, A11, and find out what the hell
+> they are, whether they're suitable for use.
+>
+> if they are, then great! these are what you wire up the STLINKv2 to,
+> according to what you decided to connect to just above.
+>
+> but for god's sake do not get this wrong, such as driving an input as
+> an output or vice-versa, or wiring up 5.0V to GND with those
+> jumper-cables.
+>
+> do *NOT* randomly upload and power up the ulx3s until this has been
+> THOROUGHLY triple-checked. or, you are entirely free to not bother
+> and to end up learning the hard way by destroying the FPGA.
+
+## Connecting the dots:
+
+litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
+
+ ("gpio", 0,
+ Subsignal"p", Pins("B11")),
+ Subsignal("n", Pins("C11")),
+ IOStandard("LVCMOS33")
+ ),
+ ("gpio", 1,
+ Subsignal("p", Pins("A10")),
+ Subsignal("n", Pins("A11")),
+ IOStandard("LVCMOS33")
+ ),
+
+ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
+
+ LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK
+ LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK
+ LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK
+ LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK
+
+ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
```
J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
GP,GN 8-13 differential bidirectional connected to BANK7
```
-``` Connecting all the dots
+Connecting all the dots:
+
+```
Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) | Label |
5 (J1_5-) | 0 | C11 | gn[0] | PCLKC0_0 |
6 (J1_5+) | 0 | B11 | gp[0] | PCLKT0_0 |
As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
+Proposed FPGA External Pin to STLINK JTAG pin connections:
-```proposed FPGA External Pin to STLINK JTAG pin connections
+```
all pin #'s have headers pins on the fpga unless denoted as (no header)
______________________________________________________________________________
| | board | | | | |
|_____________|_______|_____________|_____________|________________|___________|
```
-```complete diagram
+Complete diagram:
+```
Pins intentionally have no header or are not connected to the STLINKVT are marked
and therefore have no value are marked with 'NOT'
|_____________________________________________________________|
```
+## Images of wires on FPGA and on STLINKV2
+
pic fpga pic stlinkv2
+## Questions
+
Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG?
Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
projects / libreriscv.git / commitdiff