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diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 4d21a5752860daff00f96b80ca34c42224681295..55cb67becd411b6f8ae0aa7988e1e39678ccb612 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -368,6 +368,16 @@ This instruction is present in ARM assembler as FJCVTZS
 |--------|------|--------|-------|-------|----|------|
 |  Major | RT   | //Mode | FRA   | XO    | Rc |X-Form|
 
+**Rc=1 and OE=1**
+
+All of these insructions have an Rc=1 mode which sets CR0
+in the normal way for any instructions producing a GPR result.
+Additionally, when OE=1, if the numerical value of the FP number
+is not 100% accurately preserved (due to truncation or saturation
+and including when the FP number was NaN) then this is considered
+to be an integer Overflow condition, and CR0.SO, XER.SO and XER.OV
+are all set as normal for any GPR instructions that overflow.
+
 **Instructions**
 
 * `fcvttgw RT, FRA, Mode`