soc/cores/clock: add USIDELAYCTRL

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 44858447c3625b310d22c6aa4874c0785f169686..8e2a24bacf9eb2e92a9c26b214e971b145aec103 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -385,6 +385,23 @@ class USMMCM(USClocking):
             self.params["o_CLKOUT{}".format(n)] = clk
         self.specials += Instance("MMCME2_ADV", **self.params)
 
+
+class USIDELAYCTRL(Module):
+    def __init__(self, cd):
+        reset_counter = Signal(6, reset=63)
+        ic_reset = Signal(reset=1)
+        sync = getattr(self.sync, cd.name)
+        sync += \
+            If(reset_counter != 0,
+                reset_counter.eq(reset_counter - 1)
+            ).Else(
+                ic_reset.eq(0)
+            )
+        self.specials += Instance("IDELAYCTRL",
+            p_SIM_DEVICE="ULTRASCALE",
+            i_REFCLK=cd.clk,
+            i_RST=ic_reset)
+
 # Lattice / ECP5
 
 # TODO: