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diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 4edd00d587162e5c7483059e32080770dbd7b9db..32773ef66a015a6ff830425a5a06e6317f8fca87 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -18,7 +18,9 @@ Dynamic SIMD ALUs for maximum performance and effectiveness.
 
 # Analysis
 
-This section covers an analysis of big integer operations
+This section covers an analysis of big integer operations.  Use of
+smaller sub-operations is a given: worst-case, addition is O(N)
+whilst multiply and divide are O(N^2).
 
 ## Add and Subtract
 
@@ -52,3 +54,23 @@ Instead, Intel, in 2012, specifically added a `mulx` instruction, allowing
 both HI and LO halves of the multiply to reach registers.  If done as a
 multiply-and-accumulate this becomes quite an expensive operation:
 3 64-Bit in, 2 64-bit registers out).
+
+Long-multiplication may be performed a row at a time, starting
+with B0:
+
+    C4 C3 C2 C1 C0
+             A0xB0
+          A1xB0
+       A2xB0
+    A3xB0
+    R4 R3 R2 R1 R0
+
+* R0 contains C0 plus the LO half of A0 times B0
+* R1 contains C1 plus the LO half of A1 times B0
+  plus the HI half of A0 times B0.
+
+This would on the face of it be a 4-in operation:
+the upper half of a previous multiply, two new operands
+to multiply, and an additional accumulator (C). However if
+C is left out (and added afterwards with a Vector-Add)
+things become more manageable.