* Various MIPS test case tweaks.

Mon May 18 13:11:45 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* gas/mips/{div,ld,mul}.d: Add assembler -mcpu= flag to match
 	disassembler.
start-sanitize-r5900
	* gas/mips/break5900.[sd]: Test that break instructions generated
 	in div/etc. macro instructions are of 20-bit variety for R5900.
end-sanitize-r5900

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index addf47b7e28c17245aa54f1d40be526a5450bd9f..6a391d21710e1308ec5baa86d76fbe1a4324c251 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+Mon May 18 13:11:45 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+       * gas/mips/{div,ld,mul}.d: Add assembler -mcpu= flag to match
+       disassembler.
+start-sanitize-r5900
+       * gas/mips/break5900.[sd]: Test that break instructions generated
+       in div/etc. macro instructions are of 20-bit variety for R5900.
+end-sanitize-r5900
+
+       
 Fri May 15 14:51:01 1998  Gavin Koch  <gavin@cygnus.com>
 
        * gas/mips/mips.exp: Distinguish chains with 32-bit addresses.

diff --git a/gas/testsuite/gas/mips/break5900.s b/gas/testsuite/gas/mips/break5900.s
new file mode 100644 (file)
index 0000000..2659b73
--- /dev/null
+++ b/gas/testsuite/gas/mips/break5900.s
@@ -0,0 +1,27 @@
+# Source file used to test the 20-bit break instructions
+foo:   
+       break
+       break   0
+       break   20
+       break   40
+       break   1023
+       break   0xffff0
+       break   0xfffff
+
+# Test div macros to confirm its use of 20-bit break - from div.s testcase
+
+
+       div     $4,1
+       div     $4,$5,1
+       divu    $0,$4,$5
+       divu    $4,$5
+       divu    $4,1
+       rem     $4,$5,$6
+       remu    $4,$5,2
+       ddiv    $4,$5,$6
+       ddivu   $4,$5,2
+       drem    $4,$5,0x8000
+
+# force some padding, to make objdump consistently report that there's some
+# here...
+       .space  8