+2004-11-10 James A. Morrison <phython@gcc.gnu.org>
+
+ PR target/18230
+ (addsi3, subsi3): Set "fptype" attribute.
+ (addv2si, addv4hi, addv2hi, subv2si, subv4hi, subv2hi): New patterns.
+
2004-11-10 Steven Bosscher <stevenb@suse.de>
* basic-block.h (XMALLOC_REG_SET, XFREE_REG_SET): New.
add\t%1, %2, %0
sub\t%1, -%2, %0
fpadd32s\t%1, %2, %0"
- [(set_attr "type" "*,*,fga")])
+ [(set_attr "type" "*,*,fga")
+ (set_attr "fptype" "*,*,single")])
(define_insn "*cmp_cc_plus"
[(set (reg:CC_NOOV 100)
sub\t%1, %2, %0
add\t%1, -%2, %0
fpsub32s\t%1, %2, %0"
- [(set_attr "type" "*,*,fga")])
+ [(set_attr "type" "*,*,fga")
+ (set_attr "fptype" "*,*,single")])
(define_insn "*cmp_minus_cc"
[(set (reg:CC_NOOV 100)
"TARGET_TLS && TARGET_ARCH64"
"stx\t%0, [%1 + %2], %%tldo_add(%3)"
[(set_attr "type" "store")])
+
+;; Vector instructions.
+
+(define_insn "addv2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=e")
+ (plus:V2SI (match_operand:V2SI 1 "register_operand" "%e")
+ (match_operand:V2SI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpadd32\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+(define_insn "addv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+ (plus:V4HI (match_operand:V4HI 1 "register_operand" "%e")
+ (match_operand:V4HI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpadd16\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+;; fpadd32s is emitted by the addsi3 pattern.
+
+(define_insn "addv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=f")
+ (plus:V2HI (match_operand:V2HI 1 "register_operand" "%f")
+ (match_operand:V2HI 2 "register_operand" "f")))]
+ "TARGET_VIS"
+ "fpadd16s\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "single")])
+
+(define_insn "subv2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=e")
+ (minus:V2SI (match_operand:V2SI 1 "register_operand" "e")
+ (match_operand:V2SI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpsub32\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+(define_insn "subv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+ (minus:V4HI (match_operand:V4HI 1 "register_operand" "e")
+ (match_operand:V4HI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpsub16\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+;; fpsub32s is emitted by the subsi3 pattern.
+
+(define_insn "subv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=f")
+ (minus:V2HI (match_operand:V2HI 1 "register_operand" "f")
+ (match_operand:V2HI 2 "register_operand" "f")))]
+ "TARGET_VIS"
+ "fpsub16s\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "single")])
+2004-11-10 James A. Morrison <phython@gcc.gnu.org>
+
+ * gcc.target/sparc: New directory.
+ * gcc.target/sparc/sparc.exp: New driver.
+ * gcc.target/sparc/fpadd16.c, gcc.target/sparc/fpadd16s.c,
+ gcc.target/sparc/fpsub16.c, gcc.target/sparc/fpsub16s.c,
+ gcc.target/sparc/fpadd32.c, gcc.target/sparc/fpadd32s.c,
+ gcc.target/sparc/fpsub32.c, gcc.target/sparc/fpsub32s.c: New tests.
+
2004-11-10 Paul Brook <paul@codesourcery.com>
PR fortran/18218
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+ return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16\t%" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+ return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16s\t%" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+ return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd32\t%" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+ return foo1 () + foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpadd32s\t%" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+ return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16\t%" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+ return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16s\t%" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+ return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub32\t%" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+ return foo1 () - foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpsub32s\t%" } } */
--- /dev/null
+# Copyright (C) 1997, 2004 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a SPARC target.
+if ![istarget sparc*-*-*] then {
+ return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+ set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+ "" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish