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Merge pull request #1109 from YosysHQ/clifford/fix1106
authorClifford Wolf <clifford@clifford.at>
Wed, 19 Jun 2019 15:25:39 +0000 (17:25 +0200)
committerGitHub <noreply@github.com>
Wed, 19 Jun 2019 15:25:39 +0000 (17:25 +0200)
Add "read_verilog -pwires" feature


Trivial merge