SoCCore: set integrated rom/sram size default values in soc_core_args and use it...

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 63a6ea449c65617b7ec4a1f68feb7362b0c56cc7..fbae4668f545f784f940c928cc2182706dc237f3 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -48,14 +48,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = arty.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                         **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -81,7 +78,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
                                                self.platform.request("eth"))

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 553a2f2ab6ff554114d91adc484ba03522fc61ce..b9385f2d7b5d162d737ddafd4a1a86378e3bcde7 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM):
         platform = de0nano.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size=0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 7bb495dcb58a51a64fb9ab50a08ac2720f0196e9..1d685c750ec1f01a5bcea2e4fd1650dbe3e5ddb8 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -41,14 +41,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = genesys2.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -74,7 +71,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 8716072108ccadebbb5e4ee1233c9d090b852b34..c34b1ab0b0bcf649d39d935b9eeb3ae09e5b1df3 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -43,14 +43,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = kc705.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -76,7 +73,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
                                             self.platform.request("eth"), clk_freq=self.clk_freq)

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 1243454fab249862efa991f00f6764f2b3f69e07..ff78579cf147d9b9b1cf3bf7cd3e646ba23297cd 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -81,10 +81,7 @@ class BaseSoC(SoCSDRAM):
         platform = kcu105.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-             **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -111,7 +108,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
         self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 04f71c592f062a7f5713dd153e72e7640b17c619..e67c16da94ea390876b4a41f089ce79dc2fa5ca9 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -49,9 +49,7 @@ class BaseSoC(SoCSDRAM):
         platform = minispartan6.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size = 0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 7fecb76ab482566ddeaeb69996747960034c4dc7..90bdba024ecf2a877f487930df4555ad6e40cc22 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -46,14 +46,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = netv2.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -79,7 +76,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
                                                 self.platform.request("eth"))

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index e19c6f3a4550c94e0ccd51a03fcce0453361bf94..8999603e5b8a516f37c5a6467ab4c18505ee0d29 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -45,14 +45,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = nexys4ddr.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index fa423ac6288ffbee67718aca469ff2ffca25fd6d..b00c1886d665865388566dde64d3ab1e34380cfa 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -45,14 +45,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = nexys_video.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size  = integrated_rom_size,
-            integrated_sram_size = 0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -78,7 +75,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))

diff --git a/litex/boards/targets/pcie_screamer.py b/litex/boards/targets/pcie_screamer.py
index 809d051a6cde573881deb74ee7d125186548f6e3..f94d40fe14237b09c3ba45eeeae615d77b5e10a8 100755 (executable)
--- a/litex/boards/targets/pcie_screamer.py
+++ b/litex/boards/targets/pcie_screamer.py
@@ -39,14 +39,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = pcie_screamer.Platform()
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size=integrated_rom_size,
-            integrated_sram_size=0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index 877719ea6cf7b855012b16f87f880a37e6b4ecb4..d04dd8d28871b010a5beeb2be880256c34e7a4e9 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -19,14 +19,12 @@ from liteeth.mac import LiteEthMAC
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, platform, integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, platform, **kwargs):
         sys_clk_freq = int(1e9/platform.default_clk_period)
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size=integrated_rom_size,
-            integrated_main_ram_size=16*1024,
-            **kwargs)
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
@@ -38,7 +36,7 @@ class EthernetSoC(BaseSoC):
     }
     mem_map.update(BaseSoC.mem_map)
 
-    def __init__(self, platform, integrated_rom_size=0x10000, **kwargs):
+    def __init__(self, platform, **kwargs):
         BaseSoC.__init__(self, platform, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 94994a77f28162dbccde774870278f8180d0e167..0869069bbde44b9ac2ad90c69d9f61dd9bedfa89 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -55,9 +55,7 @@ class BaseSoC(SoCSDRAM):
         sys_clk_freq = int(50e6)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size=0x8000,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 87125712ade0b76bfd9079756db2d886dd91f5c9..fe3f0e1e888bd9c71f9d68fc50feee952b526742 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -72,13 +72,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size=integrated_rom_size,
-            **kwargs)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -105,7 +103,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, toolchain="diamond", **kwargs):
-        BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs)
+        BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(
             self.platform.request("eth_clocks"),

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 6592e1a2770677e254ee63c3378957b48893499a..8bd25f2c9872a9f607fd738dac05e685af77b5c4 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -85,7 +85,7 @@ class SoCCore(Module):
                 # CPU parameters
                 cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
                 # ROM parameters
-                integrated_rom_size=0, integrated_rom_init=[],
+                integrated_rom_size=32768, integrated_rom_init=[],
                 # SRAM parameters
                 integrated_sram_size=4096, integrated_sram_init=[],
                 # MAIN_RAM parameters
@@ -560,13 +560,13 @@ def soc_core_args(parser):
     parser.add_argument("--cpu-reset-address", default=None, type=int,
                         help="CPU reset address (default=0x00000000 or ROM)")
     # ROM parameters
-    parser.add_argument("--integrated-rom-size", default=None, type=int,
+    parser.add_argument("--integrated-rom-size", default=0x8000, type=int,
                         help="size/enable the integrated (BIOS) ROM")
     parser.add_argument("--integrated-rom-file", default=None, type=str,
-                        help="integrated (BIOS) ROM binary file")
+                        help="integrated (BIOS) ROM binary file (default=32KB)")
     # SRAM parameters
-    parser.add_argument("--integrated_sram_size", default=None,
-                        help="size/enable the integrated SRAM")
+    parser.add_argument("--integrated_sram_size", default=0x1000,
+                        help="size/enable the integrated SRAM (default=4KB)")
     # MAIN_RAM parameters
     parser.add_argument("--integrated-main-ram-size", default=None, type=int,
                         help="size/enable the integrated main RAM")