re PR target/77934 (pattern for mtvsrdd needs to use b constraint not r)

2016-10-12  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

	PR target/77934
	* config/rs6000/vmx.md (vsx_concat_<mode>): The mtvsrdd instruction
	needs a base register for arg 1.

From-SVN: r241017

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6facb484ff8fdb120ebe03a1225241f4e71e1aca..a3e779458597bc52d6df204a62bd3ce357db006a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-10-12  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
+
+       PR target/77934
+       * config/rs6000/vmx.md (vsx_concat_<mode>): The mtvsrdd instruction
+       needs a base register for arg 1.
+
 2016-10-12  Jakub Jelinek  <jakub@redhat.com>
 
        * common.opt (Wimplicit-fallthrough) Turn into alias to

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 359e424d6b4a7684b864e3b333dbed60d8eb01fb..0f650242da4a4722c9d2d221b784699a168228cc 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1938,8 +1938,8 @@
 (define_insn "vsx_concat_<mode>"
   [(set (match_operand:VSX_D 0 "gpc_reg_operand" "=<VSa>,we")
        (vec_concat:VSX_D
-        (match_operand:<VS_scalar> 1 "gpc_reg_operand" "<VS_64reg>,r")
-        (match_operand:<VS_scalar> 2 "gpc_reg_operand" "<VS_64reg>,r")))]
+        (match_operand:<VS_scalar> 1 "gpc_reg_operand" "<VS_64reg>,b")
+        (match_operand:<VS_scalar> 2 "gpc_reg_operand" "<VS_64reg>,b")))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
 {
   if (which_alternative == 0)