Keep track of bits in variable length chain, to check for taps
authorEddie Hung <eddie@fpgeh.com>
Fri, 23 Aug 2019 23:21:10 +0000 (16:21 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 23 Aug 2019 23:21:10 +0000 (16:21 -0700)
passes/pmgen/xilinx_srl.pmg

index fcfa79ea6b99c6f683211ce3ad116f9814249244..d177992089b3c5bfb86d0dd5c18968122f03cd47 100644 (file)
@@ -186,6 +186,11 @@ state <int> shiftx_width
 state <int> slice
 udata <int> minlen
 udata <vector<pair<Cell*,int>>> chain
+udata <pool<SigBit>> chain_bits
+
+code
+       chain_bits.clear();
+endcode
 
 match shiftx
        select shiftx->type.in($shiftx)
@@ -251,13 +256,20 @@ match next
        index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
        filter port(next, clk_port) == port(first, clk_port)
        filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+       filter !chain_bits.count(port(next, \D)[idx])
        set slice idx
 endmatch
 
 code
        if (next) {
+               chain_bits.insert(port(next, \Q)[slice]);
                chain.emplace_back(next, slice);
                if (GetSize(chain) < shiftx_width)
                        subpattern(tail);
        }
+finally
+       if (next) {
+               chain_bits.erase(port(next, \Q)[slice]);
+               chain.pop_back();
+       }
 endcode