}
static struct nouveau_channel_context *
-nouveau_channel_context_create(struct nouveau_device *nvdev, unsigned chipset)
+nouveau_channel_context_create(struct nouveau_device *dev)
{
struct nouveau_channel_context *nvc;
int ret;
nvc = CALLOC_STRUCT(nouveau_channel_context);
if (!nvc)
return NULL;
- nvc->chipset = chipset;
- if ((ret = nouveau_channel_alloc(nvdev, 0x8003d001, 0x8003d002,
+ if ((ret = nouveau_channel_alloc(dev, 0x8003d001, 0x8003d002,
&nvc->channel))) {
NOUVEAU_ERR("Error creating GPU channel: %d\n", ret);
nouveau_channel_context_destroy(nvc);
return NULL;
}
- switch (chipset & 0xf0) {
+ switch (dev->chipset & 0xf0) {
case 0x50:
case 0x80:
case 0x90:
__DRIscreenPrivate *driScrnPriv = driContextPriv->driScreenPriv;
struct nouveau_screen *nv_screen = driScrnPriv->private;
struct nouveau_context *nv = CALLOC_STRUCT(nouveau_context);
- struct nouveau_device_priv *nvdev;
struct pipe_context *pipe = NULL;
struct st_context *st_share = NULL;
struct nouveau_channel_context *nvc = NULL;
+ struct nouveau_device *dev = nv_screen->device;
int i, ret;
if (sharedContextPrivate) {
st_share = ((struct nouveau_context *)sharedContextPrivate)->st;
}
- /* Check for supported arch */
- if ((ret = nouveau_device_get_param(nv_screen->device,
- NOUVEAU_GETPARAM_CHIPSET_ID,
- &nv->chipset))) {
- NOUVEAU_ERR("Error determining chipset id: %d\n", ret);
- return GL_FALSE;
- }
-
- switch (nv->chipset & 0xf0) {
+ switch (dev->chipset & 0xf0) {
case 0x10:
case 0x20:
/* NV10 */
/* G80 */
break;
default:
- NOUVEAU_ERR("Unsupported chipset: NV%02x\n", (int)nv->chipset);
+ NOUVEAU_ERR("Unsupported chipset: NV%02x\n", dev->chipset);
return GL_FALSE;
}
nv->nv_screen = nv_screen;
nv->dri_screen = driScrnPriv;
- nvdev = nouveau_device(nv_screen->device);
- nvdev->ctx = driContextPriv->hHWContext;
- nvdev->lock = (drmLock *)&driScrnPriv->pSAREA->lock;
+ {
+ struct nouveau_device_priv *nvdev = nouveau_device(dev);
+
+ nvdev->ctx = driContextPriv->hHWContext;
+ nvdev->lock = (drmLock *)&driScrnPriv->pSAREA->lock;
+ }
driParseConfigFiles(&nv->dri_option_cache, &nv_screen->option_cache,
nv->dri_screen->myNum, "nouveau");
}
/*XXX: temporary - disable multi-context/single-channel on pre-NV4x */
- switch (nv->chipset & 0xf0) {
+ switch (dev->chipset & 0xf0) {
case 0x40:
case 0x60:
/* NV40 class */
}
if (!nvc) {
- nvc = nouveau_channel_context_create(&nvdev->base, nv->chipset);
+ nvc = nouveau_channel_context_create(dev);
if (!nvc) {
NOUVEAU_ERR("Failed initialising GPU context\n");
return GL_FALSE;
}
/* Create pipe */
- switch (nv->chipset & 0xf0) {
+ switch (dev->chipset & 0xf0) {
case 0x50:
case 0x80:
case 0x90:
unsigned nr_pctx;
struct pipe_context **pctx;
- unsigned chipset;
-
struct nouveau_channel *channel;
struct nouveau_notifier *sync_notifier;
struct nouveau_context {
struct st_context *st;
- /* Misc HW info */
- uint64_t chipset;
-
/* DRI stuff */
__DRIscreenPrivate *dri_screen;
__DRIdrawablePrivate *dri_drawable;
return ret;
}
+ {
+ uint64_t value;
+
+ ret = nouveau_device_get_param(&nvdev->base,
+ NOUVEAU_GETPARAM_CHIPSET_ID,
+ &value);
+ if (ret) {
+ nouveau_device_close((void *)&nvdev);
+ return ret;
+ }
+ nvdev->base.chipset = value;
+ }
+
*dev = &nvdev->base;
return 0;
}
#define __NOUVEAU_DEVICE_H__
struct nouveau_device {
+ unsigned chipset;
};
#endif
#include "pipe/p_util.h"
#include "nouveau_context.h"
+#include "nouveau_screen.h"
#include "nouveau_winsys_pipe.h"
#include "nouveau/nouveau_winsys.h"
unsigned chipset);
struct pipe_context *(*hw_create)(struct pipe_screen *, unsigned);
struct pipe_winsys *ws;
+ unsigned chipset = nv->nv_screen->device->chipset;
if (!nvws)
return NULL;
- switch (nv->chipset & 0xf0) {
+ switch (chipset & 0xf0) {
case 0x10:
case 0x20:
hws_create = nv10_screen_create;
hw_create = nv50_create;
break;
default:
- NOUVEAU_ERR("Unknown chipset NV%02x\n", (int)nv->chipset);
+ NOUVEAU_ERR("Unknown chipset NV%02x\n", chipset);
return NULL;
}
ws = nouveau_create_pipe_winsys(nv);
if (!nvc->pscreen)
- nvc->pscreen = hws_create(ws, nvws, nv->chipset);
+ nvc->pscreen = hws_create(ws, nvws, chipset);
nvc->pctx[nv->pctx_id] = hw_create(nvc->pscreen, nv->pctx_id);
return nvc->pctx[nv->pctx_id];
}
nouveau_surface_channel_create_nv04(struct nouveau_channel_context *nvc)
{
struct nouveau_channel *chan = nvc->channel;
- unsigned class;
+ unsigned chipset = nvc->channel->device->chipset, class;
int ret;
if ((ret = nouveau_grobj_alloc(chan, nvc->next_handle++, 0x39,
NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
OUT_RING (chan, nvc->sync_notifier->handle);
- class = nvc->chipset < 0x10 ? NV04_CONTEXT_SURFACES_2D :
- NV10_CONTEXT_SURFACES_2D;
+ class = chipset < 0x10 ? NV04_CONTEXT_SURFACES_2D :
+ NV10_CONTEXT_SURFACES_2D;
if ((ret = nouveau_grobj_alloc(chan, nvc->next_handle++, class,
&nvc->NvCtxSurf2D))) {
NOUVEAU_ERR("Error creating 2D surface object: %d\n", ret);
OUT_RING (chan, nvc->channel->vram->handle);
OUT_RING (chan, nvc->channel->vram->handle);
- class = nvc->chipset < 0x10 ? NV04_IMAGE_BLIT :
- NV12_IMAGE_BLIT;
+ class = chipset < 0x10 ? NV04_IMAGE_BLIT : NV12_IMAGE_BLIT;
if ((ret = nouveau_grobj_alloc(chan, nvc->next_handle++, class,
&nvc->NvImageBlit))) {
NOUVEAU_ERR("Error creating blit object: %d\n", ret);
NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
- switch (nvc->chipset & 0xf0) {
+ switch (chipset & 0xf0) {
case 0x00:
case 0x10:
class = NV04_SWIZZLED_SURFACE;
BIND_RING (chan, nvc->NvSwzSurf, nvc->next_subchannel++);
- if (nvc->chipset < 0x10) {
+ if (chipset < 0x10) {
class = NV04_SCALED_IMAGE_FROM_MEMORY;
} else
- if (nvc->chipset < 0x40) {
+ if (chipset < 0x40) {
class = NV10_SCALED_IMAGE_FROM_MEMORY;
} else {
class = NV40_SCALED_IMAGE_FROM_MEMORY;