opcodes/
authorMaciej W. Rozycki <macro@linux-mips.org>
Tue, 18 Sep 2012 14:19:04 +0000 (14:19 +0000)
committerMaciej W. Rozycki <macro@linux-mips.org>
Tue, 18 Sep 2012 14:19:04 +0000 (14:19 +0000)
* micromips-opc.c (micromips_opcodes): Correct the encoding of
the "swxc1" instruction.

gas/testsuite/
* gas/mips/micromips.d: Correct the disassembly of SWXC1.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips@24k-triple-stores-1.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.

gas/testsuite/ChangeLog
gas/testsuite/gas/mips/micromips-trap.d
gas/testsuite/gas/mips/micromips.d
gas/testsuite/gas/mips/micromips@24k-triple-stores-1.d
gas/testsuite/gas/mips/micromips@mips4-fp.d
opcodes/ChangeLog
opcodes/micromips-opc.c

index e381c0004d8fec7438234d23b7c9226d849c8d4d..c3f40c2b998756a6723a4b844399b60f0d7c6340 100644 (file)
@@ -1,3 +1,10 @@
+2012-09-18  Chao-ying Fu  <fu@mips.com>
+
+       * gas/mips/micromips.d: Correct the disassembly of SWXC1.
+       * gas/mips/micromips-trap.d: Likewise.
+       * gas/mips/micromips@24k-triple-stores-1.d: Likewise.
+       * gas/mips/micromips@mips4-fp.d: Likewise.
+
 2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * gas/aarch64/crypto.d (#as): Update for v8->v8-A change.
index 461f23b282d0aabd6268fd20f970b3902b680acb..b97c29f7f86ed834383488696fd0b7590ba1db85 100644 (file)
@@ -6504,14 +6504,14 @@ Disassembly of section \.text:
 [ 0-9a-f]+:    41a1 1234       lui     at,0x1234
 [ 0-9a-f]+:    0081 0950       addu    at,at,a0
 [ 0-9a-f]+:    9861 5678       swc1    \$f3,22136\(at\)
-[ 0-9a-f]+:    5400 0048       lwxc1   \$f0,zero\(zero\)
-[ 0-9a-f]+:    5402 0048       lwxc1   \$f0,zero\(v0\)
-[ 0-9a-f]+:    541f 0048       lwxc1   \$f0,zero\(ra\)
-[ 0-9a-f]+:    545f 0048       lwxc1   \$f0,v0\(ra\)
-[ 0-9a-f]+:    57ff 0048       lwxc1   \$f0,ra\(ra\)
-[ 0-9a-f]+:    57ff 0848       lwxc1   \$f1,ra\(ra\)
-[ 0-9a-f]+:    57ff 1048       lwxc1   \$f2,ra\(ra\)
-[ 0-9a-f]+:    57ff f848       lwxc1   \$f31,ra\(ra\)
+[ 0-9a-f]+:    5400 0088       swxc1   \$f0,zero\(zero\)
+[ 0-9a-f]+:    5402 0088       swxc1   \$f0,zero\(v0\)
+[ 0-9a-f]+:    541f 0088       swxc1   \$f0,zero\(ra\)
+[ 0-9a-f]+:    545f 0088       swxc1   \$f0,v0\(ra\)
+[ 0-9a-f]+:    57ff 0088       swxc1   \$f0,ra\(ra\)
+[ 0-9a-f]+:    57ff 0888       swxc1   \$f1,ra\(ra\)
+[ 0-9a-f]+:    57ff 1088       swxc1   \$f2,ra\(ra\)
+[ 0-9a-f]+:    57ff f888       swxc1   \$f31,ra\(ra\)
 [ 0-9a-f]+:    5401 233b       trunc\.l\.s     \$f0,\$f1
 [ 0-9a-f]+:    57df 233b       trunc\.l\.s     \$f30,\$f31
 [ 0-9a-f]+:    5442 233b       trunc\.l\.s     \$f2,\$f2
index 1de9dab2405129a0a1307db3882b575ae9e31cc7..af437f5ec27f88d679ad6635bf01fba1c20b9bdd 100644 (file)
@@ -6576,14 +6576,14 @@ Disassembly of section \.text:
 [ 0-9a-f]+:    41a1 1234       lui     at,0x1234
 [ 0-9a-f]+:    0081 0950       addu    at,at,a0
 [ 0-9a-f]+:    9861 5678       swc1    \$f3,22136\(at\)
-[ 0-9a-f]+:    5400 0048       lwxc1   \$f0,zero\(zero\)
-[ 0-9a-f]+:    5402 0048       lwxc1   \$f0,zero\(v0\)
-[ 0-9a-f]+:    541f 0048       lwxc1   \$f0,zero\(ra\)
-[ 0-9a-f]+:    545f 0048       lwxc1   \$f0,v0\(ra\)
-[ 0-9a-f]+:    57ff 0048       lwxc1   \$f0,ra\(ra\)
-[ 0-9a-f]+:    57ff 0848       lwxc1   \$f1,ra\(ra\)
-[ 0-9a-f]+:    57ff 1048       lwxc1   \$f2,ra\(ra\)
-[ 0-9a-f]+:    57ff f848       lwxc1   \$f31,ra\(ra\)
+[ 0-9a-f]+:    5400 0088       swxc1   \$f0,zero\(zero\)
+[ 0-9a-f]+:    5402 0088       swxc1   \$f0,zero\(v0\)
+[ 0-9a-f]+:    541f 0088       swxc1   \$f0,zero\(ra\)
+[ 0-9a-f]+:    545f 0088       swxc1   \$f0,v0\(ra\)
+[ 0-9a-f]+:    57ff 0088       swxc1   \$f0,ra\(ra\)
+[ 0-9a-f]+:    57ff 0888       swxc1   \$f1,ra\(ra\)
+[ 0-9a-f]+:    57ff 1088       swxc1   \$f2,ra\(ra\)
+[ 0-9a-f]+:    57ff f888       swxc1   \$f31,ra\(ra\)
 [ 0-9a-f]+:    5401 233b       trunc\.l\.s     \$f0,\$f1
 [ 0-9a-f]+:    57df 233b       trunc\.l\.s     \$f30,\$f31
 [ 0-9a-f]+:    5442 233b       trunc\.l\.s     \$f2,\$f2
index 15f38953b72fd443569b977f67edb7a2cafac983..99757b9b62316c199742942383ac649b265c947c 100644 (file)
@@ -58,11 +58,11 @@ Disassembly of section \.text:
  *[0-9a-f]+:   209d a010       sdc2    \$4,16\(sp\)
  *[0-9a-f]+:   20bd a018       sdc2    \$5,24\(sp\)
  *[0-9a-f]+:   20dd a020       sdc2    \$6,32\(sp\)
- *[0-9a-f]+:   5528 0048       lwxc1   \$f0,t1\(t0\)
- *[0-9a-f]+:   5548 0848       lwxc1   \$f1,t2\(t0\)
- *[0-9a-f]+:   5568 1048       lwxc1   \$f2,t3\(t0\)
- *[0-9a-f]+:   5588 1848       lwxc1   \$f3,t4\(t0\)
- *[0-9a-f]+:   55a8 2048       lwxc1   \$f4,t5\(t0\)
+ *[0-9a-f]+:   5528 0088       swxc1   \$f0,t1\(t0\)
+ *[0-9a-f]+:   5548 0888       swxc1   \$f1,t2\(t0\)
+ *[0-9a-f]+:   5568 1088       swxc1   \$f2,t3\(t0\)
+ *[0-9a-f]+:   5588 1888       swxc1   \$f3,t4\(t0\)
+ *[0-9a-f]+:   55a8 2088       swxc1   \$f4,t5\(t0\)
  *[0-9a-f]+:   5528 0108       sdxc1   \$f0,t1\(t0\)
  *[0-9a-f]+:   5548 1108       sdxc1   \$f2,t2\(t0\)
  *[0-9a-f]+:   5568 2108       sdxc1   \$f4,t3\(t0\)
index 35131b9e93c1c4042738325ec36696fdfe4f23dd..73581bed9d171700fb80492aaa2273fa486cd8b2 100644 (file)
@@ -45,6 +45,6 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 5486 423b    rsqrt\.d        \$f4,\$f6
 [0-9a-f]+ <[^>]*> 5486 023b    rsqrt\.s        \$f4,\$f6
 [0-9a-f]+ <[^>]*> 5485 2108    sdxc1   \$f4,a0\(a1\)
-[0-9a-f]+ <[^>]*> 5485 2048    lwxc1   \$f4,a0\(a1\)
+[0-9a-f]+ <[^>]*> 5485 2088    swxc1   \$f4,a0\(a1\)
 [0-9a-f]+ <[^>]*> 0c00         nop
        \.\.\.
index ab543ca441be89f9ea3b81bb7418418d8768b18c..ca493db357b0ae6f0afc05a2b7738bd41d4b5cf7 100644 (file)
@@ -1,3 +1,8 @@
+2012-09-18  Chao-ying Fu  <fu@mips.com>
+
+       * micromips-opc.c (micromips_opcodes): Correct the encoding of
+       the "swxc1" instruction.
+
 2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
index b4982cc5e0dd3f79ec2fb6183c3d7acc9bf05a17..5e71dfb5f911dd538ec3cbdee193679acae9bca2 100644 (file)
@@ -911,7 +911,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"invalidate", "t,~(b)",0x60009000, 0xfc00f000,        SM|RD_b|RD_t,           0,              I1      }, /* same */
 {"invalidate", "t,o(b)",0,    (int) M_SWR_OB,  INSN_MACRO,             0,              I1      },
 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,  INSN_MACRO,             0,              I1      },
-{"swxc1",   "D,t(b)",  0x54000048, 0xfc0007ff, SM|RD_t|RD_b|FP_S,      RD_D,           I1      },
+{"swxc1",   "D,t(b)",  0x54000088, 0xfc0007ff, SM|RD_t|RD_b|FP_S,      RD_D,           I1      },
 {"sync_acquire", "",   0x00116b7c, 0xffffffff, NODS,                   0,              I1      },
 {"sync_mb", "",                0x00106b7c, 0xffffffff, NODS,                   0,              I1      },
 {"sync_release", "",   0x00126b7c, 0xffffffff, NODS,                   0,              I1      },