Cleanup
authorEddie Hung <eddie@fpgeh.com>
Fri, 12 Jul 2019 23:06:14 +0000 (16:06 -0700)
committerEddie Hung <eddie@fpgeh.com>
Sat, 13 Jul 2019 02:30:18 +0000 (19:30 -0700)
passes/techmap/abc9.cc

index 5da5efcdc19a7509c8e8c2848e6e36f547b40de0..867b06cbeb7d14be56c4ff95f4bfa897453d9e9d 100644 (file)
@@ -611,21 +611,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                                                RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
                                                                RTLIL::Const::from_string("01"));
                                                bit2sinks[cell->getPort("\\A")].push_back(cell);
+                                               cell_stats["$lut"]++;
                                        }
-                                       else {
+                                       else
                                                push_inverters.emplace_back(c, driver_lut);
-                                               continue;
-                                       }
+                                       continue;
                                }
-                               else {
-                                       cell = module->addCell(remap_name(c->name), "$_NOT_");
-                                       cell->setPort("\\A", RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset));
-                                       cell->setPort("\\Y", RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset));
-                                       cell_stats[RTLIL::unescape_id(c->type)]++;
+                               else
                                        log_abort();
-                               }
                                if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
-                               cell_stats[RTLIL::unescape_id(c->type)]++;
                                continue;
                        }
                        cell_stats[RTLIL::unescape_id(c->type)]++;