Added `imac` config for CPUs which implements the most basic working riscv32imac...

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 21f7ce5d566a97011e19b6d6306dac319a00f999..5497bac853a850717e11eafac1224b271f5eeaea 100644 (file)
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -61,6 +61,7 @@ CPU_VARIANTS = {
     "minimal" : ["min",],
     "lite" : ["light", "zephyr", "nuttx"],
     "standard": [None, "std"],
+    "imac": [],
     "full": [],
     "linux" : [],
     "linuxd" : [],

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 8e27e5d3fcd3e9316f5ed4146e6931e751250aa9..1ed0494b5f2251f1a9ef36c7ceb069367851344b 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -25,6 +25,8 @@ CPU_VARIANTS = {
     "lite+debug":       "VexRiscv_LiteDebug",
     "standard":         "VexRiscv",
     "standard+debug":   "VexRiscv_Debug",
+    "imac":             "VexRiscv_IMAC",
+    "imac+debug":       "VexRiscv_IMACDebug",
     "full":             "VexRiscv_Full",
     "full+debug":       "VexRiscv_FullDebug",
     "linux":            "VexRiscv_Linux",
@@ -47,6 +49,8 @@ GCC_FLAGS = {
     "lite+debug":       "-march=rv32i      -mabi=ilp32",
     "standard":         "-march=rv32im     -mabi=ilp32",
     "standard+debug":   "-march=rv32im     -mabi=ilp32",
+    "imac":             "-march=rv32imac   -mabi=ilp32",
+    "imac+debug":       "-march=rv32imac   -mabi=ilp32",
     "full":             "-march=rv32im     -mabi=ilp32",
     "full+debug":       "-march=rv32im     -mabi=ilp32",
     "linux":            "-march=rv32ima    -mabi=ilp32",