[BRW_OPCODE_ASR] = {
.name = "asr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
},
- /* Reserved - 13-15 */
+ /* Reserved - 13 */
+ [BRW_OPCODE_ROR] = {
+ .name = "ror", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11),
+ },
+ [BRW_OPCODE_ROL] = {
+ .name = "rol", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11),
+ },
[BRW_OPCODE_CMP] = {
.name = "cmp", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
},
ALU2(SHL)
ALU1(DIM)
ALU2(ASR)
+ALU2(ROL)
+ALU2(ROR)
ALU3(CSEL)
ALU1(F32TO16)
ALU1(F16TO32)
BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
/* Reserved - 11 */
BRW_OPCODE_ASR = 12,
- /* Reserved - 13-15 */
+ /* Reserved - 13 */
+ BRW_OPCODE_ROR = 14, /**< Gen11+ */
+ BRW_OPCODE_ROL = 15, /**< Gen11+ */
BRW_OPCODE_CMP = 16,
BRW_OPCODE_CMPN = 17,
BRW_OPCODE_CSEL = 18, /**< Gen8+ */
ALU2(SHL)
ALU1(DIM)
ALU2(ASR)
+ALU2(ROL)
+ALU2(ROR)
ALU3(CSEL)
ALU1(FRC)
ALU1(RNDD)
ALU1(RNDE)
ALU1(RNDU)
ALU1(RNDZ)
+ ALU2(ROL)
+ ALU2(ROR)
ALU2(SAD2)
ALU2_ACC(SADA2)
ALU2(SEL)
case BRW_OPCODE_SHL:
brw_SHL(p, dst, src[0], src[1]);
break;
+ case BRW_OPCODE_ROL:
+ assert(devinfo->gen >= 11);
+ assert(src[0].type == dst.type);
+ brw_ROL(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_ROR:
+ assert(devinfo->gen >= 11);
+ assert(src[0].type == dst.type);
+ brw_ROR(p, dst, src[0], src[1]);
+ break;
case BRW_OPCODE_F32TO16:
assert(devinfo->gen >= 7);
brw_F32TO16(p, dst, src[0]);