rl78.md (mulsi3_g13): Correct values for MDBL and MDBH registers.

	* config/rl78/rl78.md (mulsi3_g13): Correct values for MDBL and
	MDBH registers.

From-SVN: r195020

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2e662e840ae1177759f31ef04ceb9bb9634919b3..78eb7c07b206325eaeed4c64c0be93159d01862f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -2,6 +2,8 @@
 
        * config/rl78/rl78.c (rl78_expand_prologue): Always select
        register bank 0 at the start of an interrupt handler.
+       * config/rl78/rl78.md (mulsi3_g13): Correct values for MDBL and
+       MDBH registers.
 
 2013-01-08  James Greenhalgh  <james.greenhalgh@arm.com>
 

diff --git a/gcc/config/rl78/rl78.md b/gcc/config/rl78/rl78.md
index 0910a009a245eab33b7a76cf14557648640976e8..6448b9046ec9648dcdd89aa55c132548e31f07bc 100644 (file)
--- a/gcc/config/rl78/rl78.md
+++ b/gcc/config/rl78/rl78.md
@@ -273,10 +273,10 @@
   )
 
 ;; 0xFFFF0 is MDAL.  0xFFFF2 is MDAH.
-;; 0xFFFF4 is MDBL.  0xFFFF6 is MDBH.
+;; 0xFFFF6 is MDBL.  0xFFFF4 is MDBH.
 ;; 0xF00E0 is MDCL.  0xF00E2 is MDCH.
 ;; 0xF00E8 is MDUC.
-;; Warning: this matches the documentation, not the silicon.
+;; Warning: this matches the silicon not the documentation.
 (define_insn "mulsi3_g13"
   [(set (match_operand:SI          0 "register_operand" "=&v")
        (mult:SI (match_operand:SI 1 "nonmemory_operand" "vi")
@@ -291,12 +291,12 @@
        movw    ax, %h2
        movw    0xffff2, ax     ; MDAH
        nop     ; mdb = mdal * mdah
-       movw    ax, 0xffff4     ; MDBL
+       movw    ax, 0xffff6     ; MDBL
        movw    %h0, ax
 
        mov     a, #0x40
        mov     !0xf00e8, a     ; MDUC
-       movw    ax, 0xffff6     ; MDBH
+       movw    ax, 0xffff4     ; MDBH
        movw    !0xf00e0, ax    ; MDCL
        movw    ax, #0
        movw    !0xf00e2, ax    ; MDCL